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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - [CI][RESUME]igt@kms_big_fb@yf-tiled-addfb|igt@kms_concurrent@pipe-a|igt@kms_dp_dsc@basic-dsc-enable-edp - incomplete - system hang"
href="https://bugs.freedesktop.org/show_bug.cgi?id=112036#c2">Comment # 2</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - [CI][RESUME]igt@kms_big_fb@yf-tiled-addfb|igt@kms_concurrent@pipe-a|igt@kms_dp_dsc@basic-dsc-enable-edp - incomplete - system hang"
href="https://bugs.freedesktop.org/show_bug.cgi?id=112036">bug 112036</a>
from <span class="vcard"><a class="email" href="mailto:manasi.d.navare@intel.com" title="Manasi <manasi.d.navare@intel.com>"> <span class="fn">Manasi</span></a>
</span></b>
<pre>Assessment:
All the boot logs show that for a hotplug on DP-1 , it asks for AUX B power
enable for Combo PHY AUX power well enable which is not set in
HSW_PWR_WELL_CTL_STATE and hence power well timeout. This can occur if TBT DP
tunnel is down which looks like a case with this TGL board.
Manasi</pre>
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