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<b><a class="bz_bug_link
bz_status_NEEDINFO "
title="NEEDINFO - Commit 0c06fa15600 (Add support of BT.2020 Colorimetry to DP MSA) causing 4K monitor corruption"
href="https://bugs.freedesktop.org/show_bug.cgi?id=112212#c4">Comment # 4</a>
on <a class="bz_bug_link
bz_status_NEEDINFO "
title="NEEDINFO - Commit 0c06fa15600 (Add support of BT.2020 Colorimetry to DP MSA) causing 4K monitor corruption"
href="https://bugs.freedesktop.org/show_bug.cgi?id=112212">bug 112212</a>
from <span class="vcard"><a class="email" href="mailto:elongbug@gmail.com" title="Mun, Gwan-gyeong <elongbug@gmail.com>"> <span class="fn">Mun, Gwan-gyeong</span></a>
</span></b>
<pre>Hi Ken,
I am Gwan-gyeong aka. G.G.
Can you check with your drm-tip includes this commit or not?
ommit d4a415dcda35d298b0048eb9c1a9bc04a5007fe0
Author: Ville Syrjälä <<a href="mailto:ville.syrjala@linux.intel.com">ville.syrjala@linux.intel.com</a>>
Date: Tue Oct 15 22:05:38 2019 +0300
drm/i915: Fix MST oops due to MSA changes
The MSA MISC computation now depends on the connector state, and
we do it from the DDI .pre_enable() hook. All that is fine for
DP SST but with MST we don't actually pass the connector state
to the dig port's .pre_enable() hook which leads to an oops.
Need to think more how to solve this in a cleaner fashion, but
for now let's just add a NULL check to stop the oopsing.
Cc: Gwan-gyeong Mun <<a href="mailto:gwan-gyeong.mun@intel.com">gwan-gyeong.mun@intel.com</a>>
Cc: Uma Shankar <<a href="mailto:uma.shankar@intel.com">uma.shankar@intel.com</a>>
Fixes: 0c06fa156006 ("drm/i915/dp: Add support of BT.2020 Colorimetry to DP
MSA")
Signed-off-by: Ville Syrjälä <<a href="mailto:ville.syrjala@linux.intel.com">ville.syrjala@linux.intel.com</a>>
Link:
<a href="https://patchwork.freedesktop.org/patch/msgid/20191015190538.27539-1-ville.syrjala@linux.intel.com">https://patchwork.freedesktop.org/patch/msgid/20191015190538.27539-1-ville.syrjala@linux.intel.com</a>
Reviewed-by: Uma Shankar <<a href="mailto:uma.shankar@intel.com">uma.shankar@intel.com</a>>
Reviewed-by: Gwan-gyeong Mun <<a href="mailto:gwan-gyeong.mun@intel.com">gwan-gyeong.mun@intel.com</a>></pre>
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