✗ Fi.CI.BAT: failure for series starting with [01/18] drm/i915: Set crtc_state->lane_count for HDMI

[Patchwork]

== Series Details ==

Series: series starting with [01/18] drm/i915: Set crtc_state->lane_count for HDMI
URL   : https://patchwork.freedesktop.org/series/5967/
State : failure

== Summary ==

Series 5967v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/5967/revisions/1/mbox/

Test gem_busy:
        Subgroup basic-blt:
                skip       -> PASS       (bsw-nuc-2)
Test gem_exec_suspend:
        Subgroup basic-s3:
                pass       -> INCOMPLETE (hsw-gt2)
Test kms_flip:
        Subgroup basic-flip-vs-wf_vblank:
                fail       -> PASS       (byt-nuc)

bdw-nuci7        total:192  pass:180  dwarn:0   dfail:0   fail:0   skip:12 
bdw-ultra        total:192  pass:169  dwarn:0   dfail:0   fail:0   skip:23 
bsw-nuc-2        total:191  pass:152  dwarn:0   dfail:0   fail:0   skip:39 
byt-nuc          total:191  pass:153  dwarn:0   dfail:0   fail:0   skip:38 
hsw-brixbox      total:192  pass:168  dwarn:0   dfail:0   fail:0   skip:24 
hsw-gt2          total:125  pass:110  dwarn:0   dfail:0   fail:0   skip:14 
ivb-t430s        total:192  pass:164  dwarn:0   dfail:0   fail:0   skip:28 
skl-i7k-2        total:192  pass:167  dwarn:0   dfail:0   fail:0   skip:25 
skl-nuci5        total:192  pass:181  dwarn:0   dfail:0   fail:0   skip:11 
snb-dellxps      total:192  pass:154  dwarn:0   dfail:0   fail:0   skip:38 
snb-x220t        total:192  pass:154  dwarn:0   dfail:0   fail:1   skip:37 

Results at /archive/results/CI_IGT_test/Private_28/

30468e0d25064b544b8da9d14fd7727fdd650064 drm-intel-nightly: 2016y-04m-19d-16h-24m-23s UTC integration manifest
9d82e9a drm/i915: Store VLV LPF coefficient and ssc flag in dpll_hw_state
d879f45 drm/i915: Move dpll dividers into dpll_hw_state
0d873cd drm/i915: Remove intel_limit_t typedef
bec42aa drm/i915: Remove intel_range_t and intel_p2_t typedefs
67b7113 drm/i915: Remove intel_clock_t typedef
de6a43c drm/i915: Merge vlv/chv _prepare_pll() with their enable counterpart
dc0012a drm/i915: Move dpio part of chv_prepare_pll() to intel_dpio_phy.c
c0a7c34 drm/i915: Move dpio part of vlv_prepare_pll() to intel_dpio_phy.c
21f7e4d drm/i915: Move VLV HDMI lane reset work around logic to intel_dpio_phy.c
f73534e drm/i915: Unduplicate pre encoder enabling phy code
d17a59d drm/i915: Unduplicate VLV phy pre pll enabling code
20a10cd drm/i915: Undiplicate VLV signal level code
8f0fcc6 drm/i915: Unduplicate CHV encoders' post pll disable code
6ad9416 drm/i915: Unduplicate CHV pre-encoder enabling phy logic
ecbf3dd drm/i915: Unduplicate CHV phy-releated pre pll enabling code
a7dc316 drm/i915: Unduplicate chv_data_lane_soft_reset()
24a9c87 drm/i915: Unduplicate CHV signal level code
4adae9a drm/i915: Set crtc_state->lane_count for HDMI