drm/i915: Add support for SKL/BXT 9.18 GuC Firmware for SLPC
Sagar Arun Kamble
sagar.a.kamble at intel.com
Mon Aug 22 04:19:27 UTC 2016
v2: Checkpatch update.
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 71 ++++++++++++++++++--------------
drivers/gpu/drm/i915/intel_guc_loader.c | 12 +++---
drivers/gpu/drm/i915/intel_slpc.c | 27 +++++++-----
drivers/gpu/drm/i915/intel_slpc.h | 73 ++++++++++++++++++++++-----------
4 files changed, 110 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f0474f1..83f26ef 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1359,10 +1359,10 @@ static int i915_slpc_info(struct seq_file *m, void *unused)
struct page *page;
void *pv = NULL;
struct slpc_shared_data data;
+ struct slpc_task_state_data *task_data;
int i, value;
enum slpc_global_state global_state;
enum slpc_platform_sku platform_sku;
- enum slpc_host_os host_os;
enum slpc_power_plan power_plan;
enum slpc_power_source power_source;
@@ -1379,11 +1379,6 @@ static int i915_slpc_info(struct seq_file *m, void *unused)
data = *(struct slpc_shared_data *) pv;
kunmap_atomic(pv);
- seq_printf(m, "SLPC Version: %d.%d.%d (0x%8x)\n",
- data.slpc_version >> 16,
- (data.slpc_version >> 8) & 0xFF,
- data.slpc_version & 0xFF,
- data.slpc_version);
seq_printf(m, "shared data size: %d\n", data.shared_data_size);
global_state = (enum slpc_global_state) data.global_state;
@@ -1442,20 +1437,6 @@ static int i915_slpc_info(struct seq_file *m, void *unused)
seq_printf(m, "slice count: %d\n",
data.platform_info.slice_count);
- host_os = (enum slpc_host_os) data.platform_info.host_os;
- seq_printf(m, "host OS: %d (", host_os);
- switch (host_os) {
- case SLPC_HOST_OS_UNDEFINED:
- seq_puts(m, "undefined)\n");
- break;
- case SLPC_HOST_OS_WINDOWS_8:
- seq_puts(m, "Windows 8)\n");
- break;
- default:
- seq_puts(m, "unknown)\n");
- break;
- }
-
seq_printf(m, "power plan/source: 0x%x\n\tplan:\t",
data.platform_info.power_plan_source);
power_plan = (enum slpc_power_plan) SLPC_POWER_PLAN(
@@ -1502,17 +1483,45 @@ static int i915_slpc_info(struct seq_file *m, void *unused)
data.platform_info.P1_freq * 50,
data.platform_info.Pe_freq * 50,
data.platform_info.Pn_freq * 50);
- seq_printf(m, "RAPL package power limits:\n\t0x%08x\n\t0x%08x\n",
- data.platform_info.package_rapl_limit_high,
- data.platform_info.package_rapl_limit_low);
- seq_printf(m, "task state data: 0x%08x\n",
- data.task_state_data);
- seq_printf(m, "\tturbo active: %d\n",
- (data.task_state_data & 1));
- seq_printf(m, "\tdfps stall possible: %d\n\tgame mode: %d\n\tdfps target fps: %d\n",
- (data.task_state_data & 2),
- (data.task_state_data & 4),
- (data.task_state_data >> 3) & 0xFF);
+ task_data = &data.task_state_data;
+ seq_printf(m, "task state data: 0x%08x 0x%08x\n",
+ task_data->bitfield1, task_data->bitfield2);
+
+ seq_printf(m, "\tgtperf task active: %s\n",
+ yesno(task_data->gtperf_task_active));
+ seq_printf(m, "\tgtperf stall possible: %s\n",
+ yesno(task_data->gtperf_stall_possible));
+ seq_printf(m, "\tgtperf gaming mode: %s\n",
+ yesno(task_data->gtperf_gaming_mode));
+ seq_printf(m, "\tgtperf target fps: %d\n",
+ task_data->gtperf_target_fps);
+
+ seq_printf(m, "\tdcc task active: %s\n",
+ yesno(task_data->dcc_task_active));
+ seq_printf(m, "\tin dcc: %s\n",
+ yesno(task_data->in_dcc));
+ seq_printf(m, "\tin dct: %s\n",
+ yesno(task_data->in_dct));
+ seq_printf(m, "\tfreq switch active: %d\n",
+ task_data->freq_switch_active);
+
+ seq_printf(m, "\tibc enabled: %s\n",
+ yesno(task_data->ibc_enabled));
+ seq_printf(m, "\tibc active: %s\n",
+ yesno(task_data->ibc_active));
+ seq_printf(m, "\tpg1 enabled: %s\n",
+ yesno(task_data->pg1_enabled));
+ seq_printf(m, "\tpg1 active: %s\n",
+ yesno(task_data->pg1_active));
+
+ seq_printf(m, "\tunslice max freq: %d\n",
+ task_data->freq_unslice_max);
+ seq_printf(m, "\tunslice min freq: %d\n",
+ task_data->freq_unslice_min);
+ seq_printf(m, "\tslice max freq: %d\n",
+ task_data->freq_slice_max);
+ seq_printf(m, "\tslice min freq: %d\n",
+ task_data->freq_slice_min);
seq_puts(m, "override parameter bitfield\n");
for (i = 0; i < SLPC_OVERRIDE_BITFIELD_SIZE; i++)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 13ffd47..4ec5a4d 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -59,11 +59,11 @@
*
*/
-#define SKL_FW_MAJOR 6
-#define SKL_FW_MINOR 1
+#define SKL_FW_MAJOR 9
+#define SKL_FW_MINOR 18
-#define BXT_FW_MAJOR 8
-#define BXT_FW_MINOR 7
+#define BXT_FW_MAJOR 9
+#define BXT_FW_MINOR 18
#define KBL_FW_MAJOR 9
#define KBL_FW_MINOR 14
@@ -164,8 +164,8 @@ static void sanitize_slpc_option(struct drm_i915_private *dev_priv)
if (!i915.enable_guc_submission)
i915.enable_slpc = 0;
- if ((IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 6))
- || (IS_BROXTON(dev_priv) && (guc_fw->guc_fw_major_found != 8))) {
+ if ((IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 9))
+ || (IS_BROXTON(dev_priv) && (guc_fw->guc_fw_major_found != 9))) {
DRM_INFO("SLPC not supported with current GuC firmware\n");
i915.enable_slpc = 0;
}
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 6883f44..5ab8362 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -229,14 +229,12 @@ static void slpc_shared_data_init(struct drm_i915_private *dev_priv)
data = kmap_atomic(page);
memset(data, 0, sizeof(struct slpc_shared_data));
- data->slpc_version = SLPC_VERSION;
data->shared_data_size = sizeof(struct slpc_shared_data);
data->global_state = (u32)SLPC_GLOBAL_STATE_NOT_RUNNING;
data->platform_info.platform_sku =
(u8)slpc_get_platform_sku(dev_priv);
data->platform_info.slice_count =
(u8)slpc_get_slice_count(dev_priv);
- data->platform_info.host_os = (u8)SLPC_HOST_OS_WINDOWS_8;
data->platform_info.power_plan_source =
(u8)SLPC_POWER_PLAN_SOURCE(SLPC_POWER_PLAN_BALANCED,
SLPC_POWER_SOURCE_AC);
@@ -246,10 +244,6 @@ static void slpc_shared_data_init(struct drm_i915_private *dev_priv)
data->platform_info.P1_freq = (u8)(msr_value >> 8);
data->platform_info.Pe_freq = (u8)(msr_value >> 40);
data->platform_info.Pn_freq = (u8)(msr_value >> 48);
- rdmsrl(MSR_PKG_POWER_LIMIT, msr_value);
- data->platform_info.package_rapl_limit_high =
- (u32)(msr_value >> 32);
- data->platform_info.package_rapl_limit_low = (u32)msr_value;
kunmap_atomic(data);
}
@@ -320,17 +314,28 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv)
SLPC_PARAM_TASK_DISABLE_DCC);
intel_slpc_set_param(dev_priv,
- SLPC_PARAM_GLOBAL_DISABLE_IA_GT_BALANCING,
- 1);
+ SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING,
+ 0);
+
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS,
+ 0);
+
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING,
+ 0);
intel_slpc_set_param(dev_priv,
- SLPC_PARAM_DFPS_THRESHOLD_MAX_FPS,
+ SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO,
0);
intel_slpc_set_param(dev_priv,
- SLPC_PARAM_DFPS_DISABLE_FRAMERATE_STALLING,
- 1);
+ SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE,
+ 0);
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
+ 0);
}
void intel_slpc_reset(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index a2161b0b..c773617 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -24,10 +24,6 @@
#ifndef _INTEL_SLPC_H_
#define _INTEL_SLPC_H_
-#define SLPC_MAJOR_VER 2
-#define SLPC_MINOR_VER 4
-#define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
-
enum slpc_status {
SLPC_STATUS_OK = 0,
SLPC_STATUS_ERROR = 1,
@@ -45,14 +41,13 @@ enum slpc_status {
SLPC_STATUS_VALUE_ALREADY_SET = 13,
SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
SLPC_STATUS_VALUE_NOT_CHANGED = 15,
- SLPC_STATUS_MISMATCHING_VERSION = 16,
- SLPC_STATUS_MEMIO_ERROR = 17,
- SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 18,
- SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 19,
- SLPC_STATUS_NO_EVENT_QUEUED = 20,
- SLPC_STATUS_OUT_OF_SPACE = 21,
- SLPC_STATUS_TIMEOUT = 22,
- SLPC_STATUS_NO_LOCK = 23,
+ SLPC_STATUS_MEMIO_ERROR = 16,
+ SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 17,
+ SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 18,
+ SLPC_STATUS_NO_EVENT_QUEUED = 19,
+ SLPC_STATUS_OUT_OF_SPACE = 20,
+ SLPC_STATUS_TIMEOUT = 21,
+ SLPC_STATUS_NO_LOCK = 22,
};
enum slpc_event_id {
@@ -80,13 +75,16 @@ enum slpc_param_id {
SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
- SLPC_PARAM_DFPS_THRESHOLD_MAX_FPS = 10,
+ SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10,
SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
- SLPC_PARAM_DFPS_DISABLE_FRAMERATE_STALLING = 12,
+ SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12,
SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
- SLPC_PARAM_GLOBAL_DISABLE_IA_GT_BALANCING = 16,
+ SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16,
+ SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17,
+ SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE = 18,
+ SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19,
};
#define SLPC_PARAM_TASK_DEFAULT 0
@@ -103,11 +101,6 @@ enum slpc_global_state {
SLPC_GLOBAL_STATE_ERROR = 5
};
-enum slpc_host_os {
- SLPC_HOST_OS_UNDEFINED = 0,
- SLPC_HOST_OS_WINDOWS_8 = 1,
-};
-
enum slpc_platform_sku {
SLPC_PLATFORM_SKU_UNDEFINED = 0,
SLPC_PLATFORM_SKU_ULX = 1,
@@ -140,25 +133,55 @@ enum slpc_power_source {
struct slpc_platform_info {
u8 platform_sku;
u8 slice_count;
- u8 host_os;
+ u8 reserved;
u8 power_plan_source;
u8 P0_freq;
u8 P1_freq;
u8 Pe_freq;
u8 Pn_freq;
- u32 package_rapl_limit_high;
- u32 package_rapl_limit_low;
+ u32 reserved1;
+ u32 reserved2;
} __packed;
+struct slpc_task_state_data {
+ union {
+ u32 bitfield1;
+ struct {
+ u32 gtperf_task_active:1;
+ u32 gtperf_stall_possible:1;
+ u32 gtperf_gaming_mode:1;
+ u32 gtperf_target_fps:8;
+ u32 dcc_task_active:1;
+ u32 in_dcc:1;
+ u32 in_dct:1;
+ u32 freq_switch_active:1;
+ u32 ibc_enabled:1;
+ u32 ibc_active:1;
+ u32 pg1_enabled:1;
+ u32 pg1_active:1;
+ u32 reserved:13;
+ };
+ };
+ union {
+ u32 bitfield2;
+ struct {
+ u32 freq_unslice_max:8;
+ u32 freq_unslice_min:8;
+ u32 freq_slice_max:8;
+ u32 freq_slice_min:8;
+ };
+ };
+};
+
#define SLPC_MAX_OVERRIDE_PARAMETERS 192
#define SLPC_OVERRIDE_BITFIELD_SIZE ((SLPC_MAX_OVERRIDE_PARAMETERS + 31) / 32)
struct slpc_shared_data {
- u32 slpc_version;
+ u32 reserved;
u32 shared_data_size;
u32 global_state;
struct slpc_platform_info platform_info;
- u32 task_state_data;
+ struct slpc_task_state_data task_state_data;
u32 override_parameters_set_bits[SLPC_OVERRIDE_BITFIELD_SIZE];
u32 override_parameters_values[SLPC_MAX_OVERRIDE_PARAMETERS];
} __packed;
--
1.9.1
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