[PATCH v5 02/28] drm/i915: Remove RPM suspend dependency on rps.enabled and related changes

[Sagar Arun Kamble]

For Gen9, RPM suspend is failing if rps.enabled=false. This is needed for
other platforms as RC6 and RPS enabling is indicated by rps.enabled.
RPM Suspend depends only on RC6, so we need to remove the check of rps.enabled.
For Gen9 RC6 and RPS enabling is separated hence do rps.enabled check only
for non-Gen9 platforms. Once RC6 and RPS enabling is separated for other GENs
this check can be completely removed.
Moved setting of rps.enabled to platform level functions as there is case of
disabling of RPS in gen9_enable_rps.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 10 +++++++++-
 drivers/gpu/drm/i915/intel_pm.c | 21 ++++++++++++++++++---
 2 files changed, 27 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c9abf91..3e808cf 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2700,9 +2700,17 @@ static int intel_runtime_suspend(struct device *device)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret;
 
-	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
+	if (WARN_ON_ONCE(!intel_enable_rc6()))
 		return -ENODEV;
 
+	/*
+	 * Once RC6 and RPS enabling is separated for non-GEN9 platforms
+	 * below check should be removed.
+	*/
+	if (!IS_GEN9(dev))
+		if (WARN_ON_ONCE(!dev_priv->rps.enabled))
+			return -ENODEV;
+
 	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
 		return -ENODEV;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 96529a6..75f53f3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4944,6 +4944,7 @@ static void gen9_disable_rps(struct drm_i915_private *dev_priv)
 
 	/* RP SW Mode Control will be needed for SLPC, Hence not clearing.*/
 	I915_WRITE(GEN6_RP_CONTROL, rp_ctl & GEN6_RP_MEDIA_MODE_MASK);
+	dev_priv->rps.enabled = false;
 }
 
 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
@@ -4951,11 +4952,16 @@ static void gen6_disable_rps(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 	I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
 	I915_WRITE(GEN6_RP_CONTROL, 0);
+
+	dev_priv->rps.enabled = false;
+
 }
 
 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE(GEN6_RC_CONTROL, 0);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
@@ -4967,6 +4973,8 @@ static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = false;
 }
 
 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
@@ -5194,6 +5202,8 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv)
 	gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
@@ -5341,6 +5351,8 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv)
 	gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
@@ -5449,6 +5461,8 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
 	}
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void __gen6_update_ring_freq(struct drm_i915_private *dev_priv)
@@ -5971,6 +5985,8 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
 	valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
@@ -6060,6 +6076,8 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
 	valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	dev_priv->rps.enabled = true;
 }
 
 static unsigned long intel_pxfreq(u32 vidfreq)
@@ -6615,7 +6633,6 @@ void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 		else
 			gen6_disable_rps(dev_priv);
 
-		dev_priv->rps.enabled = false;
 		mutex_unlock(&dev_priv->rps.hw_lock);
 	}
 }
@@ -6653,8 +6670,6 @@ static void intel_gen6_powersave_work(struct work_struct *work)
 	WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
 	WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
 
-	dev_priv->rps.enabled = true;
-
 	gen6_enable_rps_interrupts(dev_priv);
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
-- 
1.9.1