[FOR_CI 03/15] drm/i915/tdr: Update reset_in_progress to account for engine reset
Arun Siluvery
arun.siluvery at linux.intel.com
Mon Jul 4 09:30:58 UTC 2016
Now that we track reset progress using separate set of flags, update it to
account for engine reset as well.
A bit corresponding engine->id is set if reset is in progress for that
engine. Bit0 is reserved for full gpu reset.
Also add helper function to report engine reset count.
Signed-off-by: Arun Siluvery <arun.siluvery at linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 36 +++++++++++++++++++++++++++++++++++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7d8f8c1..d757ed9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1415,6 +1415,9 @@ struct i915_gpu_error {
#define I915_RESET_IN_PROGRESS_FLAG 1
#define I915_WEDGED (1 << 31)
+ /* extending the idea of reset_counter to engine reset */
+ atomic_t engine_reset_counter[I915_NUM_ENGINES];
+
/**
* Waitqueue to signal when the reset has completed. Used by clients
* that wait for dev_priv->mm.wedged to settle.
@@ -3297,9 +3300,16 @@ static inline u32 i915_reset_counter(struct i915_gpu_error *error)
return atomic_read(&error->global_reset_counter);
}
+static inline unsigned
+intel_engine_reset_flag(enum intel_engine_id id)
+{
+ return 1 << (id + 1);
+}
+
+/* indicates the progress of engine reset or full gpu reset */
static inline bool __i915_reset_in_progress(u32 flags)
{
- return unlikely(flags & I915_RESET_IN_PROGRESS_FLAG);
+ return unlikely(flags & ~I915_WEDGED);
}
static inline bool __i915_reset_in_progress_or_wedged(u32 flags)
@@ -3312,6 +3322,11 @@ static inline bool __i915_terminally_wedged(u32 flags)
return unlikely(flags & I915_WEDGED);
}
+static inline bool i915_full_gpu_reset_in_progress(struct i915_gpu_error *error)
+{
+ return unlikely(atomic_read(&error->reset_flags) & I915_RESET_IN_PROGRESS_FLAG);
+}
+
static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
{
return __i915_reset_in_progress(atomic_read(&error->reset_flags));
@@ -3332,6 +3347,25 @@ static inline u32 i915_reset_count(struct i915_gpu_error *error)
return i915_reset_counter(error);
}
+static inline bool __i915_engine_reset_in_progress(u32 reset_flags,
+ enum intel_engine_id id)
+{
+ return unlikely(reset_flags & intel_engine_reset_flag(id));
+}
+
+static inline bool i915_engine_reset_in_progress(struct i915_gpu_error *error,
+ struct intel_engine_cs *engine)
+{
+ return __i915_engine_reset_in_progress(atomic_read(&error->reset_flags),
+ engine->id);
+}
+
+static inline u32 i915_engine_reset_count(struct i915_gpu_error *error,
+ struct intel_engine_cs *engine)
+{
+ return atomic_read(&error->engine_reset_counter[engine->id]);
+}
+
static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
{
return dev_priv->gpu_error.stop_rings == 0 ||
--
1.9.1
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