[PATCH 17/28] drm/i915/slpc: Notification of Display mode change
Sagar Arun Kamble
sagar.a.kamble at intel.com
Wed Jul 6 17:37:59 UTC 2016
GuC SLPC needs to be sent data related to Active pipes, refresh rates,
widi pipes, fullscreen pipes related via host to GuC display mode
change event. Based on this, SLPC will track FPS on active pipes.
This patch defines the events and implements trigger of the events.
v2: Addressed review comments from Paulo and Ville. Changed the way
display mode information is collected in intel_atomic_commit. Coupled
display mode change event with SLPC enable/reset event. Updated inactive
crtc state in display mode data. Updated refresh rate and vsync_ft_usec
calculations to get more accurate value. (Paulo)
v2(torourke): Updates suggested by Paulo: replace HAS_SLPC with
intel_slpc_active. Return void instead of ignored error code.
v3: Addressed checkpatch issues. (Sagar)
Commit message update and bitmask op changes in display mode events.
(Nick)
Added check for mode parameters clock, htotal, vtotal. (Jon)
v5: Addressed precision issue with calculation of vsync_ft_usec. (Sagar)
Moved to display mode notification out of rps.hw_lock block as expected
locking sequence is - &dev->mode_config.mutex --> crtc_ww_class_mutex
--> &dev_priv->rps.hw_lock. Addressed rpm relaated ordering for notifying
display information. This was indicated in CI BAT.
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke at intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 4 +-
drivers/gpu/drm/i915/intel_pm.c | 4 +
drivers/gpu/drm/i915/intel_slpc.c | 169 +++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_slpc.h | 3 +
4 files changed, 179 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 88e899b..38ef27d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13890,8 +13890,10 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
drm_atomic_helper_commit_hw_done(state);
- if (intel_state->modeset)
+ if (intel_state->modeset) {
+ intel_slpc_update_atomic_commit_info(dev_priv, state);
intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
+ }
mutex_lock(&dev->struct_mutex);
drm_atomic_helper_cleanup_planes(dev, state);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5b6df89..0fb8715 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6697,6 +6697,10 @@ static void intel_gen6_powersave_work(struct work_struct *work)
mutex_unlock(&dev_priv->rps.hw_lock);
+ /* Notify initial display mode information to SLPC */
+ if (intel_slpc_active(dev_priv))
+ intel_slpc_update_display_mode_info(dev_priv);
+
intel_runtime_pm_put(dev_priv);
}
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 4c9ab01..2648faa 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -67,6 +67,23 @@ static void host2guc_slpc_shutdown(struct drm_i915_private *dev_priv)
host2guc_slpc(dev_priv, data, 4);
}
+static void host2guc_slpc_display_mode_change(struct drm_i915_private *dev_priv)
+{
+ u32 data[3 + SLPC_MAX_NUM_OF_PIPES];
+ int i;
+ struct intel_slpc_display_mode_event_params *display_mode_params;
+
+ display_mode_params = &dev_priv->guc.slpc.display_mode_params;
+ data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+ data[1] = SLPC_EVENT(SLPC_EVENT_DISPLAY_MODE_CHANGE,
+ SLPC_MAX_NUM_OF_PIPES + 1);
+ data[2] = display_mode_params->global_data;
+ for(i = 0; i < SLPC_MAX_NUM_OF_PIPES; ++i)
+ data[3+i] = display_mode_params->per_pipe_info[i].data;
+
+ host2guc_slpc(dev_priv, data, 3 + SLPC_MAX_NUM_OF_PIPES);
+}
+
static u8 slpc_get_platform_sku(struct drm_i915_gem_object *obj)
{
struct drm_device *dev = obj->base.dev;
@@ -189,3 +206,155 @@ void intel_slpc_reset(struct drm_i915_private *dev_priv)
host2guc_slpc_shutdown(dev_priv);
dev_priv->guc.slpc.enabled = false;
}
+
+void intel_slpc_update_display_mode_info(struct drm_i915_private *dev_priv)
+{
+ struct intel_crtc *intel_crtc;
+ struct intel_display_pipe_info *per_pipe_info;
+ struct intel_slpc_display_mode_event_params *cur_params, old_params;
+ bool notify = false;
+
+ if (!intel_slpc_active(dev_priv))
+ return;
+
+ /* Copy display mode parameters for comparison */
+ cur_params = &dev_priv->guc.slpc.display_mode_params;
+ old_params.global_data = cur_params->global_data;
+ cur_params->global_data = 0;
+
+ intel_runtime_pm_get(dev_priv);
+ drm_modeset_lock_all(dev_priv->dev);
+
+ for_each_intel_crtc(dev_priv->dev, intel_crtc) {
+ per_pipe_info = &cur_params->per_pipe_info[intel_crtc->pipe];
+ old_params.per_pipe_info[intel_crtc->pipe].data =
+ per_pipe_info->data;
+ per_pipe_info->data = 0;
+
+ if (intel_crtc->active) {
+ struct drm_display_mode *mode = &intel_crtc->base.mode;
+
+ if (mode->clock == 0 || mode->htotal == 0 ||
+ mode->vtotal == 0) {
+ DRM_DEBUG_DRIVER(
+ "Display Mode Info not sent to SLPC\n");
+ drm_modeset_unlock_all(dev_priv->dev);
+ intel_runtime_pm_put(dev_priv);
+ return;
+ }
+ /* FIXME: Update is_widi based on encoder */
+ per_pipe_info->is_widi = 0;
+ per_pipe_info->refresh_rate =
+ (u32)(((u64)mode->clock * 1000) /
+ ((u64)mode->htotal * (u64)mode->vtotal));
+ per_pipe_info->vsync_ft_usec =
+ (u32)(((u64)mode->htotal * (u64)mode->vtotal * 1000) /
+ (u64)mode->clock);
+
+ cur_params->active_pipes_bitmask |=
+ (1 << intel_crtc->pipe);
+ cur_params->vbi_sync_on_pipes |=
+ (1 << intel_crtc->pipe);
+ } else {
+ cur_params->active_pipes_bitmask &=
+ ~(1 << intel_crtc->pipe);
+ cur_params->vbi_sync_on_pipes &=
+ ~(1 << intel_crtc->pipe);
+ }
+
+ if (old_params.per_pipe_info[intel_crtc->pipe].data !=
+ per_pipe_info->data)
+ notify = true;
+ }
+
+ drm_modeset_unlock_all(dev_priv->dev);
+
+ cur_params->num_active_pipes =
+ hweight32(cur_params->active_pipes_bitmask);
+
+ /*
+ * Compare old display mode with current mode.
+ * Notify SLPC if it is changed.
+ */
+ if (cur_params->global_data != old_params.global_data)
+ notify = true;
+
+ if (notify)
+ host2guc_slpc_display_mode_change(dev_priv);
+
+ intel_runtime_pm_put(dev_priv);
+}
+
+void intel_slpc_update_atomic_commit_info(struct drm_i915_private *dev_priv,
+ struct drm_atomic_state *state)
+{
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *crtc_state;
+ struct intel_display_pipe_info *per_pipe_info;
+ struct intel_slpc_display_mode_event_params *cur_params, old_params;
+ bool notify = false;
+ int i;
+
+ if (!intel_slpc_active(dev_priv))
+ return;
+
+ /* Copy display mode parameters for comparison */
+ cur_params = &dev_priv->guc.slpc.display_mode_params;
+ old_params.global_data = cur_params->global_data;
+
+ for_each_crtc_in_state(state, crtc, crtc_state, i) {
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ per_pipe_info = &cur_params->per_pipe_info[intel_crtc->pipe];
+ old_params.per_pipe_info[intel_crtc->pipe].data =
+ per_pipe_info->data;
+
+ per_pipe_info->data = 0;
+ cur_params->active_pipes_bitmask &=
+ ~(1 << intel_crtc->pipe);
+ cur_params->vbi_sync_on_pipes &=
+ ~(1 << intel_crtc->pipe);
+
+ if (crtc_state->active) {
+ struct drm_display_mode *mode = &crtc->mode;
+
+ if (mode->clock == 0 || mode->htotal == 0 ||
+ mode->vtotal == 0) {
+ DRM_DEBUG_DRIVER(
+ "Display Mode Info not sent to SLPC\n");
+ return;
+ }
+
+ /* FIXME: Update is_widi based on encoder */
+ per_pipe_info->is_widi = 0;
+ per_pipe_info->refresh_rate =
+ (u32)(((u64)mode->clock * 1000) /
+ ((u64)mode->htotal * (u64)mode->vtotal));
+ per_pipe_info->vsync_ft_usec =
+ (u32)(((u64)mode->htotal * (u64)mode->vtotal * 1000) /
+ (u64)mode->clock);
+
+ cur_params->active_pipes_bitmask |=
+ (1 << intel_crtc->pipe);
+ cur_params->vbi_sync_on_pipes |=
+ (1 << intel_crtc->pipe);
+ }
+
+ if (old_params.per_pipe_info[intel_crtc->pipe].data !=
+ per_pipe_info->data)
+ notify = true;
+ }
+
+ cur_params->num_active_pipes =
+ hweight32(cur_params->active_pipes_bitmask);
+
+ /*
+ * Compare old display mode with current mode.
+ * Notify SLPC if it is changed.
+ */
+ if (cur_params->global_data != old_params.global_data)
+ notify = true;
+
+ if (notify)
+ host2guc_slpc_display_mode_change(dev_priv);
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 68232ef..0ebdcaa 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -153,5 +153,8 @@ void intel_slpc_suspend(struct drm_i915_private *dev_priv);
void intel_slpc_disable(struct drm_i915_private *dev_priv);
void intel_slpc_enable(struct drm_i915_private *dev_priv);
void intel_slpc_reset(struct drm_i915_private *dev_priv);
+void intel_slpc_update_display_mode_info(struct drm_i915_private *dev_priv);
+void intel_slpc_update_atomic_commit_info(struct drm_i915_private *dev_priv,
+ struct drm_atomic_state *state);
#endif
--
1.9.1
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