[PATCH 6/6] drm/i915: Move dplls into struct intel_dpll_mgr
Ander Conselvan de Oliveira
ander.conselvan.de.oliveira at intel.com
Wed Jun 1 07:20:24 UTC 2016
Move DPLLs from dev_priv to struct intel_dpll_mgr. This allows the DPLL
init code to be simplified, avoiding a few copies while moving more DPLL
related code closer together.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira at intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 +-
drivers/gpu/drm/i915/i915_drv.h | 13 +-
drivers/gpu/drm/i915/intel_atomic.c | 5 +-
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 19 ++-
drivers/gpu/drm/i915/intel_dpll_mgr.c | 301 +++++++++++++++++++---------------
drivers/gpu/drm/i915/intel_dpll_mgr.h | 33 ++++
7 files changed, 227 insertions(+), 151 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e4f2c55..73c7b10 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3265,11 +3265,12 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
int i;
drm_modeset_lock_all(dev);
- for (i = 0; i < dev_priv->num_shared_dpll; i++) {
- struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
+ for (i = 0; i < dpll_mgr->num_shared_dpll; i++) {
+ struct intel_shared_dpll *pll = &dpll_mgr->shared_dplls[i];
seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 96d5034..3ae6785 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1817,6 +1817,7 @@ struct drm_i915_private {
struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
+ /* cdclk state is protected by connection_mutex */
unsigned int fsb_freq, mem_freq, is_ddr3;
unsigned int skl_preferred_vco_freq;
unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
@@ -1875,17 +1876,7 @@ struct drm_i915_private {
struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif
- /* dpll and cdclk state is protected by connection_mutex */
- int num_shared_dpll;
- struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
- const struct intel_dpll_mgr *dpll_mgr;
-
- /*
- * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
- * Must be global rather than per dpll, because on some platforms
- * plls share registers.
- */
- struct mutex dpll_lock;
+ struct intel_dpll_mgr *dpll_mgr;
unsigned int active_crtcs;
unsigned int min_pixclk[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index 50ff90a..8e9b8b0 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -268,11 +268,12 @@ static void
intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
struct intel_shared_dpll_config *shared_dpll)
{
+ struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
enum intel_dpll_id i;
/* Copy shared dpll state */
- for (i = 0; i < dev_priv->num_shared_dpll; i++) {
- struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
+ for (i = 0; i < dpll_mgr->num_shared_dpll; i++) {
+ struct intel_shared_dpll *pll = &dpll_mgr->shared_dplls[i];
shared_dpll[i] = pll->config;
}
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 022b41d..bf0d920 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -954,7 +954,7 @@ static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
if (WARN_ON(dpll == DPLL_ID_PRIVATE))
return 0;
- pll = &dev_priv->shared_dplls[dpll];
+ pll = &dev_priv->dpll_mgr->shared_dplls[dpll];
state = &pll->config.hw_state;
clock.m1 = 2;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f8f352d..3949cc9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8396,7 +8396,7 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
}
/* Check if any DPLLs are using the SSC source */
- for (i = 0; i < dev_priv->num_shared_dpll; i++) {
+ for (i = 0; i < dev_priv->dpll_mgr->num_shared_dpll; i++) {
u32 temp = I915_READ(PCH_DPLL(i));
if (!(temp & DPLL_VCO_ENABLE))
@@ -10128,6 +10128,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
&pipe_config->dpll_hw_state));
}
+
/*
* Haswell has only FDI/PCH transcoder A. It is which is connected to
* DDI E. So just check whether this pipe is wired to DDI E and whether
@@ -13213,10 +13214,12 @@ static void
verify_disabled_dpll_state(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
int i;
- for (i = 0; i < dev_priv->num_shared_dpll; i++)
- verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
+ for (i = 0; i < dpll_mgr->num_shared_dpll; i++)
+ verify_single_dpll_state(dev_priv, &dpll_mgr->shared_dplls[i],
+ NULL, NULL);
}
static void
@@ -15901,6 +15904,7 @@ static void readout_plane_state(struct intel_crtc *crtc)
static void intel_modeset_readout_hw_state(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
enum pipe pipe;
struct intel_crtc *crtc;
struct intel_encoder *encoder;
@@ -15947,8 +15951,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
crtc->active ? "enabled" : "disabled");
}
- for (i = 0; i < dev_priv->num_shared_dpll; i++) {
- struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
+ for (i = 0; i < dpll_mgr->num_shared_dpll; i++) {
+ struct intel_shared_dpll *pll = &dpll_mgr->shared_dplls[i];
pll->on = pll->funcs.get_hw_state(dev_priv, pll,
&pll->config.hw_state);
@@ -16054,6 +16058,7 @@ static void
intel_modeset_setup_hw_state(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
enum pipe pipe;
struct intel_crtc *crtc;
struct intel_encoder *encoder;
@@ -16075,8 +16080,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
intel_modeset_update_connector_atomic_state(dev);
- for (i = 0; i < dev_priv->num_shared_dpll; i++) {
- struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
+ for (i = 0; i < dpll_mgr->num_shared_dpll; i++) {
+ struct intel_shared_dpll *pll = &dpll_mgr->shared_dplls[i];
if (!pll->on || pll->active_mask)
continue;
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 0aec560..2a32abf 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -54,7 +54,7 @@ struct intel_shared_dpll *
intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
enum intel_dpll_id id)
{
- return &dev_priv->shared_dplls[id];
+ return &dev_priv->dpll_mgr->shared_dplls[id];
}
/* For ILK+ */
@@ -83,14 +83,14 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
*/
void intel_prepare_shared_dpll(struct intel_crtc *crtc)
{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
struct intel_shared_dpll *pll = crtc->config->shared_dpll;
if (WARN_ON(pll == NULL))
return;
- mutex_lock(&dev_priv->dpll_lock);
+ mutex_lock(&dpll_mgr->dpll_lock);
WARN_ON(!pll->config.crtc_mask);
if (!pll->active_mask) {
DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
@@ -99,7 +99,7 @@ void intel_prepare_shared_dpll(struct intel_crtc *crtc)
pll->funcs.prepare(dev_priv, pll);
}
- mutex_unlock(&dev_priv->dpll_lock);
+ mutex_unlock(&dpll_mgr->dpll_lock);
}
/**
@@ -110,8 +110,7 @@ void intel_prepare_shared_dpll(struct intel_crtc *crtc)
*/
void intel_enable_shared_dpll(struct intel_crtc *crtc)
{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll = crtc->config->shared_dpll;
unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base);
unsigned old_mask;
@@ -119,7 +118,7 @@ void intel_enable_shared_dpll(struct intel_crtc *crtc)
if (WARN_ON(pll == NULL))
return;
- mutex_lock(&dev_priv->dpll_lock);
+ mutex_lock(&dev_priv->dpll_mgr->dpll_lock);
old_mask = pll->active_mask;
if (WARN_ON(!(pll->config.crtc_mask & crtc_mask)) ||
@@ -144,7 +143,7 @@ void intel_enable_shared_dpll(struct intel_crtc *crtc)
pll->on = true;
out:
- mutex_unlock(&dev_priv->dpll_lock);
+ mutex_unlock(&dev_priv->dpll_mgr->dpll_lock);
}
/**
@@ -167,7 +166,7 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc)
if (pll == NULL)
return;
- mutex_lock(&dev_priv->dpll_lock);
+ mutex_lock(&dev_priv->dpll_mgr->dpll_lock);
if (WARN_ON(!(pll->active_mask & crtc_mask)))
goto out;
@@ -187,7 +186,7 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc)
pll->on = false;
out:
- mutex_unlock(&dev_priv->dpll_lock);
+ mutex_unlock(&dev_priv->dpll_mgr->dpll_lock);
}
static struct intel_shared_dpll *
@@ -197,6 +196,7 @@ intel_find_shared_dpll(struct intel_crtc *crtc,
enum intel_dpll_id range_max)
{
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+ struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
struct intel_shared_dpll *pll;
struct intel_shared_dpll_config *shared_dpll;
enum intel_dpll_id i;
@@ -204,7 +204,7 @@ intel_find_shared_dpll(struct intel_crtc *crtc,
shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
for (i = range_min; i <= range_max; i++) {
- pll = &dev_priv->shared_dplls[i];
+ pll = &dpll_mgr->shared_dplls[i];
/* Only want to check enabled timings first */
if (shared_dpll[i].crtc_mask == 0)
@@ -223,7 +223,7 @@ intel_find_shared_dpll(struct intel_crtc *crtc,
/* Ok no matching timings, maybe there's a free one? */
for (i = range_min; i <= range_max; i++) {
- pll = &dev_priv->shared_dplls[i];
+ pll = &dpll_mgr->shared_dplls[i];
if (shared_dpll[i].crtc_mask == 0) {
DRM_DEBUG_KMS("[CRTC:%d:%s] allocated %s\n",
crtc->base.base.id, crtc->base.name, pll->name);
@@ -268,6 +268,7 @@ intel_reference_shared_dpll(struct intel_shared_dpll *pll,
void intel_shared_dpll_swap_state(struct drm_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->dev);
+ struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
struct intel_shared_dpll_config *shared_dpll;
struct intel_shared_dpll *pll;
enum intel_dpll_id i;
@@ -276,8 +277,8 @@ void intel_shared_dpll_swap_state(struct drm_atomic_state *state)
return;
shared_dpll = to_intel_atomic_state(state)->shared_dpll;
- for (i = 0; i < dev_priv->num_shared_dpll; i++) {
- pll = &dev_priv->shared_dplls[i];
+ for (i = 0; i < dpll_mgr->num_shared_dpll; i++) {
+ pll = &dpll_mgr->shared_dplls[i];
pll->config = shared_dpll[i];
}
}
@@ -365,13 +366,14 @@ ibx_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
struct intel_shared_dpll *pll;
enum intel_dpll_id i;
if (HAS_PCH_IBX(dev_priv)) {
/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
i = (enum intel_dpll_id) crtc->pipe;
- pll = &dev_priv->shared_dplls[i];
+ pll = &dpll_mgr->shared_dplls[i];
DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
crtc->base.base.id, crtc->base.name, pll->name);
@@ -390,13 +392,6 @@ ibx_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
return pll;
}
-static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
- .prepare = ibx_pch_dpll_prepare,
- .enable = ibx_pch_dpll_enable,
- .disable = ibx_pch_dpll_disable,
- .get_hw_state = ibx_pch_dpll_get_hw_state,
-};
-
static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
@@ -774,18 +769,6 @@ hsw_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
}
-static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
- .enable = hsw_ddi_wrpll_enable,
- .disable = hsw_ddi_wrpll_disable,
- .get_hw_state = hsw_ddi_wrpll_get_hw_state,
-};
-
-static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
- .enable = hsw_ddi_spll_enable,
- .disable = hsw_ddi_spll_disable,
- .get_hw_state = hsw_ddi_spll_get_hw_state,
-};
-
static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
@@ -803,12 +786,6 @@ static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *dev_priv,
return true;
}
-static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
- .enable = hsw_ddi_lcpll_enable,
- .disable = hsw_ddi_lcpll_disable,
- .get_hw_state = hsw_ddi_lcpll_get_hw_state,
-};
-
struct skl_dpll_regs {
i915_reg_t ctl, cfgcr1, cfgcr2;
};
@@ -1292,18 +1269,6 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
return pll;
}
-static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
- .enable = skl_ddi_pll_enable,
- .disable = skl_ddi_pll_disable,
- .get_hw_state = skl_ddi_pll_get_hw_state,
-};
-
-static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
- .enable = skl_ddi_dpll0_enable,
- .disable = skl_ddi_dpll0_disable,
- .get_hw_state = skl_ddi_dpll0_get_hw_state,
-};
-
static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
@@ -1639,12 +1604,6 @@ bxt_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
return pll;
}
-static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
- .enable = bxt_ddi_pll_enable,
- .disable = bxt_ddi_pll_disable,
- .get_hw_state = bxt_ddi_pll_get_hw_state,
-};
-
static void intel_ddi_pll_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1666,69 +1625,168 @@ static void intel_ddi_pll_init(struct drm_device *dev)
}
}
-struct dpll_info {
- const char *name;
- const int id;
- const struct intel_shared_dpll_funcs *funcs;
- uint32_t flags;
-};
+#define PCH_DPLL_FUNCS \
+ { \
+ .prepare = ibx_pch_dpll_prepare, \
+ .enable = ibx_pch_dpll_enable, \
+ .disable = ibx_pch_dpll_disable, \
+ .get_hw_state = ibx_pch_dpll_get_hw_state, \
+ }
-struct intel_dpll_mgr {
- const struct dpll_info *dpll_info;
+static struct intel_dpll_mgr pch_pll_mgr = {
+ .num_shared_dpll = 2,
+
+ .shared_dplls = {
+ [DPLL_ID_PCH_PLL_A] = {
+ .name = "PCH DPLL A",
+ .id = DPLL_ID_PCH_PLL_A,
+ .funcs = PCH_DPLL_FUNCS,
+ },
+ [DPLL_ID_PCH_PLL_B] = {
+ .name = "PCH DPLL B",
+ .id = DPLL_ID_PCH_PLL_B,
+ .funcs = PCH_DPLL_FUNCS,
+ }
+ },
- struct intel_shared_dpll *(*get_dpll)(struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state,
- struct intel_encoder *encoder);
+ .get_dpll = ibx_get_dpll,
};
-static const struct dpll_info pch_plls[] = {
- { "PCH DPLL A", DPLL_ID_PCH_PLL_A, &ibx_pch_dpll_funcs, 0 },
- { "PCH DPLL B", DPLL_ID_PCH_PLL_B, &ibx_pch_dpll_funcs, 0 },
- { NULL, -1, NULL, 0 },
-};
+#define HSW_DDI_WRPLL_FUNCS \
+ { \
+ .enable = hsw_ddi_wrpll_enable, \
+ .disable = hsw_ddi_wrpll_disable, \
+ .get_hw_state = hsw_ddi_wrpll_get_hw_state, \
+ }
-static const struct intel_dpll_mgr pch_pll_mgr = {
- .dpll_info = pch_plls,
- .get_dpll = ibx_get_dpll,
-};
+#define HSW_DDI_SPLL_FUNCS \
+ { \
+ .enable = hsw_ddi_spll_enable, \
+ .disable = hsw_ddi_spll_disable, \
+ .get_hw_state = hsw_ddi_spll_get_hw_state, \
+ }
-static const struct dpll_info hsw_plls[] = {
- { "WRPLL 1", DPLL_ID_WRPLL1, &hsw_ddi_wrpll_funcs, 0 },
- { "WRPLL 2", DPLL_ID_WRPLL2, &hsw_ddi_wrpll_funcs, 0 },
- { "SPLL", DPLL_ID_SPLL, &hsw_ddi_spll_funcs, 0 },
- { "LCPLL 810", DPLL_ID_LCPLL_810, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
- { "LCPLL 1350", DPLL_ID_LCPLL_1350, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
- { "LCPLL 2700", DPLL_ID_LCPLL_2700, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
- { NULL, -1, NULL, },
-};
+#define HSW_DDI_LCPLL_FUNCS \
+ { \
+ .enable = hsw_ddi_lcpll_enable, \
+ .disable = hsw_ddi_lcpll_disable, \
+ .get_hw_state = hsw_ddi_lcpll_get_hw_state, \
+ }
+
+static struct intel_dpll_mgr hsw_pll_mgr = {
+ .num_shared_dpll = 6,
+
+ .shared_dplls = {
+ [DPLL_ID_WRPLL1] = {
+ .name = "WRPLL 1",
+ .id = DPLL_ID_WRPLL1,
+ .funcs = HSW_DDI_WRPLL_FUNCS,
+ },
+ [DPLL_ID_WRPLL2] = {
+ .name = "WRPLL 2",
+ .id = DPLL_ID_WRPLL2,
+ .funcs = HSW_DDI_WRPLL_FUNCS,
+ },
+ [DPLL_ID_SPLL] = {
+ .name = "SPLL",
+ .id = DPLL_ID_SPLL,
+ .funcs = HSW_DDI_SPLL_FUNCS,
+ },
+ [DPLL_ID_LCPLL_810] = {
+ .name = "LCPLL 810",
+ .id = DPLL_ID_LCPLL_810,
+ .funcs = HSW_DDI_LCPLL_FUNCS,
+ .flags = INTEL_DPLL_ALWAYS_ON
+ },
+ [DPLL_ID_LCPLL_1350] = {
+ .name = "LCPLL 1350",
+ .id = DPLL_ID_LCPLL_1350,
+ .funcs = HSW_DDI_LCPLL_FUNCS,
+ .flags = INTEL_DPLL_ALWAYS_ON
+ },
+ [DPLL_ID_LCPLL_2700] = {
+ .name = "LCPLL 2700",
+ .id = DPLL_ID_LCPLL_2700,
+ .funcs = HSW_DDI_LCPLL_FUNCS,
+ .flags = INTEL_DPLL_ALWAYS_ON
+ }
+ },
-static const struct intel_dpll_mgr hsw_pll_mgr = {
- .dpll_info = hsw_plls,
.get_dpll = hsw_get_dpll,
};
-static const struct dpll_info skl_plls[] = {
- { "DPLL 0", DPLL_ID_SKL_DPLL0, &skl_ddi_dpll0_funcs, INTEL_DPLL_ALWAYS_ON },
- { "DPLL 1", DPLL_ID_SKL_DPLL1, &skl_ddi_pll_funcs, 0 },
- { "DPLL 2", DPLL_ID_SKL_DPLL2, &skl_ddi_pll_funcs, 0 },
- { "DPLL 3", DPLL_ID_SKL_DPLL3, &skl_ddi_pll_funcs, 0 },
- { NULL, -1, NULL, },
-};
+#define SKL_DDI_PLL_FUNCS \
+ { \
+ .enable = skl_ddi_pll_enable, \
+ .disable = skl_ddi_pll_disable, \
+ .get_hw_state = skl_ddi_pll_get_hw_state, \
+ }
+
+#define SKL_DDI_PLL0_FUNCS \
+ { \
+ .enable = skl_ddi_dpll0_enable, \
+ .disable = skl_ddi_dpll0_disable, \
+ .get_hw_state = skl_ddi_dpll0_get_hw_state, \
+ }
+
+static struct intel_dpll_mgr skl_pll_mgr = {
+ .num_shared_dpll = 4,
+
+ .shared_dplls = {
+ [DPLL_ID_SKL_DPLL0] = {
+ .name = "DPLL 0",
+ .id = DPLL_ID_SKL_DPLL0,
+ .funcs = SKL_DDI_PLL0_FUNCS,
+ .flags = INTEL_DPLL_ALWAYS_ON
+ },
+ [DPLL_ID_SKL_DPLL1] = {
+ .name = "DPLL 1",
+ .id = DPLL_ID_SKL_DPLL1,
+ .funcs = SKL_DDI_PLL_FUNCS,
+ },
+ [DPLL_ID_SKL_DPLL2] = {
+ .name = "DPLL 2",
+ .id = DPLL_ID_SKL_DPLL2,
+ .funcs = SKL_DDI_PLL_FUNCS,
+ },
+ [DPLL_ID_SKL_DPLL3] = {
+ .name = "DPLL 3",
+ .id = DPLL_ID_SKL_DPLL3,
+ .funcs = SKL_DDI_PLL_FUNCS,
+ }
+ },
-static const struct intel_dpll_mgr skl_pll_mgr = {
- .dpll_info = skl_plls,
.get_dpll = skl_get_dpll,
};
-static const struct dpll_info bxt_plls[] = {
- { "PORT PLL A", DPLL_ID_SKL_DPLL0, &bxt_ddi_pll_funcs, 0 },
- { "PORT PLL B", DPLL_ID_SKL_DPLL1, &bxt_ddi_pll_funcs, 0 },
- { "PORT PLL C", DPLL_ID_SKL_DPLL2, &bxt_ddi_pll_funcs, 0 },
- { NULL, -1, NULL, },
-};
+#define BXT_DDI_PLL_FUNCS \
+ { \
+ .enable = bxt_ddi_pll_enable, \
+ .disable = bxt_ddi_pll_disable, \
+ .get_hw_state = bxt_ddi_pll_get_hw_state, \
+ }
+
+static struct intel_dpll_mgr bxt_pll_mgr = {
+ .num_shared_dpll = 3,
+
+ .shared_dplls = {
+ [DPLL_ID_SKL_DPLL0] = {
+ .name = "PORT PLL A",
+ .id = DPLL_ID_SKL_DPLL0,
+ .funcs = BXT_DDI_PLL_FUNCS,
+ },
+ [DPLL_ID_SKL_DPLL1] = {
+ .name = "PORT PLL B",
+ .id = DPLL_ID_SKL_DPLL0,
+ .funcs = BXT_DDI_PLL_FUNCS,
+ },
+ [DPLL_ID_SKL_DPLL2] = {
+ .name = "PORT PLL C",
+ .id = DPLL_ID_SKL_DPLL0,
+ .funcs = BXT_DDI_PLL_FUNCS,
+ },
+ },
-static const struct intel_dpll_mgr bxt_pll_mgr = {
- .dpll_info = bxt_plls,
.get_dpll = bxt_get_dpll,
};
@@ -1741,9 +1799,7 @@ static const struct intel_dpll_mgr bxt_pll_mgr = {
void intel_shared_dpll_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- const struct intel_dpll_mgr *dpll_mgr = NULL;
- const struct dpll_info *dpll_info;
- int i;
+ struct intel_dpll_mgr *dpll_mgr;
if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
dpll_mgr = &skl_pll_mgr;
@@ -1753,28 +1809,17 @@ void intel_shared_dpll_init(struct drm_device *dev)
dpll_mgr = &hsw_pll_mgr;
else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
dpll_mgr = &pch_pll_mgr;
+ else
+ dpll_mgr = NULL;
- if (!dpll_mgr) {
- dev_priv->num_shared_dpll = 0;
- return;
- }
-
- dpll_info = dpll_mgr->dpll_info;
-
- for (i = 0; dpll_info[i].id >= 0; i++) {
- WARN_ON(i != dpll_info[i].id);
+ dev_priv->dpll_mgr = dpll_mgr;
- dev_priv->shared_dplls[i].id = dpll_info[i].id;
- dev_priv->shared_dplls[i].name = dpll_info[i].name;
- dev_priv->shared_dplls[i].funcs = *dpll_info[i].funcs;
- dev_priv->shared_dplls[i].flags = dpll_info[i].flags;
- }
+ if (!dpll_mgr)
+ return;
- dev_priv->dpll_mgr = dpll_mgr;
- dev_priv->num_shared_dpll = i;
- mutex_init(&dev_priv->dpll_lock);
+ mutex_init(&dpll_mgr->dpll_lock);
- BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
+ BUG_ON(dpll_mgr->num_shared_dpll > I915_NUM_PLLS);
/* FIXME: Move this to a more suitable place */
if (HAS_DDI(dev))
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index fa96bd3..ae6c3fa 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -181,6 +181,39 @@ struct intel_shared_dpll {
};
/**
+ * struct intel_dpll_mgr - manager for device's DPLLs
+ */
+struct intel_dpll_mgr {
+ /* dpll state is protected by connection_mutex */
+
+ /**
+ * @num_shared_dpll: number of DPLLs
+ */
+ int num_shared_dpll;
+
+ /**
+ * @shared_dplls: vector of DPLLs
+ */
+ struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
+
+ /**
+ * @dpll_lock: serializes intel_prepare_shared_dpll(),
+ * intel_enable_shared_dpll() and intel_disable_shared_dpll().
+ * Must be global rather than per dpll, because on some platforms
+ * plls share registers.
+ */
+ struct mutex dpll_lock;
+
+ /**
+ * @get_dpll: Platform specific code for getting a DPLL for a given
+ * configuration. Should only be called from intel_get_shared_dpll().
+ */
+ struct intel_shared_dpll *(*get_dpll)(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder);
+};
+
+/**
* INTEL_DPLL_ALWAYS_ON
*
* Inform the state checker that the DPLL is kept enabled even if not
--
2.5.5
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