[PATCH 08/15] drm/i915: Move dpll dividers into dpll_hw_state

Ander Conselvan de Oliveira ander.conselvan.de.oliveira at intel.com
Mon May 2 07:56:23 UTC 2016


This will be necessary to make VLV/CHV dplls "shared".

Note that for now the value of the dividers is ignoring when checking
shared dpll state, as their state readout is not wired properly for the
platforms that need it.
---
 drivers/gpu/drm/i915/intel_display.c  | 74 ++++++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_dp.c       |  3 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.h | 14 +++++++
 drivers/gpu/drm/i915/intel_drv.h      | 16 --------
 drivers/gpu/drm/i915/intel_sdvo.c     |  2 +-
 5 files changed, 64 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dc7426c..3851993 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1549,12 +1549,16 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
 		   ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
 
 	/* No need to actually set up the DPLL with DSI */
-	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) != 0)
-		vlv_phy_prepare_pll(crtc, pipe_config->dpll.n,
-				    pipe_config->dpll.m1, pipe_config->dpll.m2,
-				    pipe_config->dpll.p1, pipe_config->dpll.p2,
+	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) != 0) {
+		const struct dpll *dividers =
+			&pipe_config->dpll_hw_state.dividers;
+
+		vlv_phy_prepare_pll(crtc, dividers->n,
+				    dividers->m1, dividers->m2,
+				    dividers->p1, dividers->p2,
 				    pipe_config->port_clock,
 				    pipe_config->has_dp_encoder);
+	}
 
 	assert_pipe_disabled(dev_priv, pipe);
 
@@ -1607,11 +1611,15 @@ static void chv_enable_pll(struct intel_crtc *crtc,
 		   pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
 
 	/* No need to actually set up the DPLL with DSI */
-	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) != 0)
-		chv_phy_prepare_pll(crtc, pipe_config->dpll.n,
-				    pipe_config->dpll.m1, pipe_config->dpll.m2,
-				    pipe_config->dpll.p1, pipe_config->dpll.p2,
-				    pipe_config->dpll.vco);
+	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) != 0) {
+		const struct dpll *dividers =
+			&pipe_config->dpll_hw_state.dividers;
+
+		chv_phy_prepare_pll(crtc, dividers->n,
+				    dividers->m1, dividers->m2,
+				    dividers->p1, dividers->p2,
+				    dividers->vco);
+	}
 
 	assert_pipe_disabled(dev_priv, pipe);
 
@@ -7087,11 +7095,11 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
 	u32 fp, fp2 = 0;
 
 	if (IS_PINEVIEW(dev)) {
-		fp = pnv_dpll_compute_fp(&crtc_state->dpll);
+		fp = pnv_dpll_compute_fp(&crtc_state->dpll_hw_state.dividers);
 		if (reduced_clock)
 			fp2 = pnv_dpll_compute_fp(reduced_clock);
 	} else {
-		fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
+		fp = i9xx_dpll_compute_fp(&crtc_state->dpll_hw_state.dividers);
 		if (reduced_clock)
 			fp2 = i9xx_dpll_compute_fp(reduced_clock);
 	}
@@ -7229,7 +7237,7 @@ int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
 		return -ENOMEM;
 
 	pipe_config->base.crtc = &crtc->base;
-	pipe_config->dpll = *dpll;
+	pipe_config->dpll_hw_state.dividers = *dpll;
 
 	if (IS_CHERRYVIEW(dev)) {
 		chv_compute_dpll(crtc, pipe_config);
@@ -7268,7 +7276,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 dpll;
 	bool is_sdvo;
-	struct dpll *clock = &crtc_state->dpll;
+	struct dpll *clock = &crtc_state->dpll_hw_state.dividers;
 
 	i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
 
@@ -7343,7 +7351,7 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 dpll;
-	struct dpll *clock = &crtc_state->dpll;
+	struct dpll *clock = &crtc_state->dpll_hw_state.dividers;
 
 	i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
 
@@ -7613,7 +7621,8 @@ static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
 
 	if (!crtc_state->clock_set &&
 	    !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
-				 refclk, NULL, &crtc_state->dpll)) {
+				 refclk, NULL,
+				 &crtc_state->dpll_hw_state.dividers)) {
 		DRM_ERROR("Couldn't find PLL settings for mode!\n");
 		return -EINVAL;
 	}
@@ -7656,7 +7665,8 @@ static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
 
 	if (!crtc_state->clock_set &&
 	    !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
-				refclk, NULL, &crtc_state->dpll)) {
+				refclk, NULL,
+				&crtc_state->dpll_hw_state.dividers)) {
 		DRM_ERROR("Couldn't find PLL settings for mode!\n");
 		return -EINVAL;
 	}
@@ -7690,7 +7700,8 @@ static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
 
 	if (!crtc_state->clock_set &&
 	    !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
-				refclk, NULL, &crtc_state->dpll)) {
+				refclk, NULL,
+				&crtc_state->dpll_hw_state.dividers)) {
 		DRM_ERROR("Couldn't find PLL settings for mode!\n");
 		return -EINVAL;
 	}
@@ -7724,7 +7735,8 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
 
 	if (!crtc_state->clock_set &&
 	    !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
-				 refclk, NULL, &crtc_state->dpll)) {
+				 refclk, NULL,
+				 &crtc_state->dpll_hw_state.dividers)) {
 		DRM_ERROR("Couldn't find PLL settings for mode!\n");
 		return -EINVAL;
 	}
@@ -7745,7 +7757,8 @@ static int chv_crtc_compute_clock(struct intel_crtc *crtc,
 
 	if (!crtc_state->clock_set &&
 	    !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
-				refclk, NULL, &crtc_state->dpll)) {
+				refclk, NULL,
+				&crtc_state->dpll_hw_state.dividers)) {
 		DRM_ERROR("Couldn't find PLL settings for mode!\n");
 		return -EINVAL;
 	}
@@ -7766,7 +7779,8 @@ static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
 
 	if (!crtc_state->clock_set &&
 	    !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
-				refclk, NULL, &crtc_state->dpll)) {
+				refclk, NULL,
+				&crtc_state->dpll_hw_state.dividers)) {
 		DRM_ERROR("Couldn't find PLL settings for mode!\n");
 		return -EINVAL;
 	}
@@ -8578,6 +8592,7 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
 	struct drm_connector *connector;
 	struct drm_connector_state *connector_state;
 	struct intel_encoder *encoder;
+	struct dpll *clock = &crtc_state->dpll_hw_state.dividers;
 	u32 dpll, fp, fp2;
 	int factor, i;
 	bool is_lvds = false, is_sdvo = false;
@@ -8611,9 +8626,9 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
 	} else if (crtc_state->sdvo_tv_clock)
 		factor = 20;
 
-	fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
+	fp = i9xx_dpll_compute_fp(clock);
 
-	if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
+	if (ironlake_needs_fb_cb_tune(clock, factor))
 		fp |= FP_CB_TUNE;
 
 	if (reduced_clock) {
@@ -8641,11 +8656,11 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
 		dpll |= DPLL_SDVO_HIGH_SPEED;
 
 	/* compute bitmask from p1 value */
-	dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
+	dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
 	/* also FPA1 */
-	dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
+	dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
 
-	switch (crtc_state->dpll.p2) {
+	switch (clock->p2) {
 	case 5:
 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
 		break;
@@ -8716,7 +8731,8 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
 
 	if (!crtc_state->clock_set &&
 	    !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
-				refclk, NULL, &crtc_state->dpll)) {
+				refclk, NULL,
+				&crtc_state->dpll_hw_state.dividers)) {
 		DRM_ERROR("Couldn't find PLL settings for mode!\n");
 		return -EINVAL;
 	}
@@ -12797,9 +12813,13 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
 			"pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
 			crtc_mask, pll->config.crtc_mask);
 
+	/*
+	 * FIXME: The read out of dividers is not properly wired up, so the
+	 * comparison will be bogus.
+	 */
 	I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
 					  &dpll_hw_state,
-					  sizeof(dpll_hw_state)),
+					  sizeof(dpll_hw_state) - sizeof(dpll_hw_state.dividers)),
 			"pll hw state mismatch\n");
 }
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3633002..fb1b339 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1299,7 +1299,8 @@ intel_dp_set_clock(struct intel_encoder *encoder,
 	if (divisor && count) {
 		for (i = 0; i < count; i++) {
 			if (pipe_config->port_clock == divisor[i].clock) {
-				pipe_config->dpll = divisor[i].dpll;
+				pipe_config->dpll_hw_state.dividers =
+					divisor[i].dpll;
 				pipe_config->clock_set = true;
 				break;
 			}
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index 89c5ada..5d086f5 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -66,6 +66,18 @@ enum intel_dpll_id {
  */
 #define INTEL_DPLL_ALWAYS_ON	(1 << 0)
 
+struct dpll {
+	/* given values */
+	int n;
+	int m1, m2;
+	int p1, p2;
+	/* derived values */
+	int	dot;
+	int	vco;
+	int	m;
+	int	p;
+};
+
 struct intel_dpll_hw_state {
 	/* i9xx, pch plls */
 	uint32_t dpll;
@@ -91,6 +103,8 @@ struct intel_dpll_hw_state {
 	/* bxt */
 	uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
 		 pcsdw12;
+
+	struct dpll dividers;
 };
 
 struct intel_shared_dpll_config {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index eb10686..b955694 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -265,18 +265,6 @@ struct intel_connector {
 	struct intel_dp *mst_port;
 };
 
-struct dpll {
-	/* given values */
-	int n;
-	int m1, m2;
-	int p1, p2;
-	/* derived values */
-	int	dot;
-	int	vco;
-	int	m;
-	int	p;
-};
-
 struct intel_atomic_state {
 	struct drm_atomic_state base;
 
@@ -481,10 +469,6 @@ struct intel_crtc_state {
 	 */
 	bool bw_constrained;
 
-	/* Settings for the intel dpll used on pretty much everything but
-	 * haswell. */
-	struct dpll dpll;
-
 	/* Selected dpll when shared or NULL. */
 	struct intel_shared_dpll *shared_dpll;
 
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 2128fae..be8811a 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1101,7 +1101,7 @@ intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
 {
 	unsigned dotclock = pipe_config->port_clock;
-	struct dpll *clock = &pipe_config->dpll;
+	struct dpll *clock = &pipe_config->dpll_hw_state.dividers;
 
 	/* SDVO TV has fixed PLL values depend on its clock range,
 	   this mirrors vbios setting. */
-- 
2.4.11



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