[PATCH 19/19] fixup! WIP: chv shared pll

[Ander Conselvan de Oliveira]

---
 drivers/gpu/drm/i915/intel_display.c | 25 +++++++------------------
 1 file changed, 7 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 48b778c..509b29c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7835,6 +7835,8 @@ static bool vlv_get_pipe_config(struct intel_crtc *crtc,
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	enum intel_display_power_domain power_domain;
+	struct intel_shared_dpll *pll;
+	bool enabled;
 	uint32_t tmp;
 	bool ret;
 
@@ -7882,26 +7884,13 @@ static bool vlv_get_pipe_config(struct intel_crtc *crtc,
 		((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
 		 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
 
-	if (IS_VALLEYVIEW(dev_priv)) {
-		struct intel_shared_dpll *pll =
-			intel_get_shared_dpll_by_id(dev_priv, crtc->pipe);
-		bool enabled;
+	pll = intel_get_shared_dpll_by_id(dev_priv, crtc->pipe);
 
-		enabled = pll->funcs.get_hw_state(dev_priv, pll,
-						  &pipe_config->dpll_hw_state);
+	enabled = pll->funcs.get_hw_state(dev_priv, pll,
+					  &pipe_config->dpll_hw_state);
 
-		if (enabled)
-			pipe_config->shared_dpll = pll;
-	} else {
-		pipe_config->dpll_hw_state.dpll_md = tmp;
-
-		pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
-
-		/* Mask out read-only status bits. */
-		pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
-						     DPLL_PORTC_READY_MASK |
-						     DPLL_PORTB_READY_MASK);
-	}
+	if (enabled)
+		pipe_config->shared_dpll = pll;
 
 	if (IS_CHERRYVIEW(dev))
 		chv_crtc_clock_get(crtc, pipe_config);
-- 
2.4.11