[PATCH 15/20] fixup! WIP: vlv shared dpll

Ander Conselvan de Oliveira ander.conselvan.de.oliveira at intel.com
Tue May 3 10:40:13 UTC 2016


---
 drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++------
 1 file changed, 19 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 658a3ad..6f79d7f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7994,14 +7994,27 @@ static bool vlv_get_pipe_config(struct intel_crtc *crtc,
 	pipe_config->pixel_multiplier =
 		((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
 		 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
-	pipe_config->dpll_hw_state.dpll_md = tmp;
 
-	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
+	if (IS_VALLEYVIEW(dev_priv)) {
+		struct intel_shared_dpll *pll =
+			intel_get_shared_dpll_by_id(dev_priv, crtc->pipe);
+		bool enabled;
+
+		enabled = pll->funcs.get_hw_state(dev_priv, pll,
+						  &pipe_config->dpll_hw_state);
+
+		if (enabled)
+			pipe_config->shared_dpll = pll;
+	} else {
+		pipe_config->dpll_hw_state.dpll_md = tmp;
 
-	/* Mask out read-only status bits. */
-	pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
-					     DPLL_PORTC_READY_MASK |
-					     DPLL_PORTB_READY_MASK);
+		pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
+
+		/* Mask out read-only status bits. */
+		pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
+						     DPLL_PORTC_READY_MASK |
+						     DPLL_PORTB_READY_MASK);
+	}
 
 	if (IS_CHERRYVIEW(dev))
 		chv_crtc_clock_get(crtc, pipe_config);
-- 
2.4.11



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