[PATCH 17/17] debug pll hw state readout
Ander Conselvan de Oliveira
ander.conselvan.de.oliveira at intel.com
Tue May 3 12:43:12 UTC 2016
---
drivers/gpu/drm/i915/intel_display.c | 50 ++++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 509b29c..78df3d7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12711,6 +12711,50 @@ verify_crtc_state(struct drm_crtc *crtc,
}
static void
+dump_hw_state(struct intel_dpll_hw_state *hw_state)
+{
+ DRM_DEBUG_KMS("%x %x %x %x %x %x %x %x %x\n",
+ hw_state->dpll,
+ hw_state->dpll_md,
+ hw_state->fp0,
+ hw_state->fp1,
+ hw_state->wrpll,
+ hw_state->spll,
+ hw_state->ctrl1,
+ hw_state->cfgcr1,
+ hw_state->cfgcr2);
+
+ DRM_DEBUG_KMS("%x %x %x %x %x %x %x %x %x %x %x\n",
+ hw_state->ebb0,
+ hw_state->ebb4,
+ hw_state->pll0,
+ hw_state->pll1,
+ hw_state->pll2,
+ hw_state->pll3,
+ hw_state->pll6,
+ hw_state->pll8,
+ hw_state->pll9,
+ hw_state->pll10,
+ hw_state->pcsdw12);
+
+ DRM_DEBUG_KMS("%x %x\n",
+ hw_state->lpf,
+ hw_state->ssc);
+
+ DRM_DEBUG_KMS("%d %d %d %d %d %d %d %d %d\n",
+ hw_state->dividers.n,
+ hw_state->dividers.m1,
+ hw_state->dividers.m2,
+ hw_state->dividers.p1,
+ hw_state->dividers.p2,
+
+ hw_state->dividers.dot,
+ hw_state->dividers.vco,
+ hw_state->dividers.m,
+ hw_state->dividers.p);
+}
+
+static void
verify_single_dpll_state(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
struct drm_crtc *crtc,
@@ -12767,6 +12811,12 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
&dpll_hw_state,
sizeof(dpll_hw_state) - sizeof(dpll_hw_state.dividers)),
"pll hw state mismatch\n");
+
+ DRM_DEBUG_KMS("sw tracking:");
+ dump_hw_state(&pll->config.hw_state);
+
+ DRM_DEBUG_KMS("hw state:");
+ dump_hw_state(&dpll_hw_state);
}
static void
--
2.4.11
More information about the Intel-gfx-trybot
mailing list