[PATCH 09/19] drm/i915: Store VLV LPF coefficient and ssc flag in dpll_hw_state

Ander Conselvan de Oliveira ander.conselvan.de.oliveira at intel.com
Mon May 9 09:44:01 UTC 2016


---
 drivers/gpu/drm/i915/i915_drv.h       |  2 +-
 drivers/gpu/drm/i915/intel_display.c  | 15 +++++++++++++--
 drivers/gpu/drm/i915/intel_dpio_phy.c | 12 +++---------
 drivers/gpu/drm/i915/intel_dpll_mgr.h |  4 ++++
 4 files changed, 21 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index efbe619..475809e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3608,7 +3608,7 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
 void vlv_phy_prepare_pll(struct intel_crtc *crtc, u32 bestn,
 			 u32 bestm1, u32 bestm2, u32 bestp1, u32 bestp2,
-			 int port_clock, bool dp);
+			 u32 lpf, bool use_ssc_source);
 
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 49ef999..4845adc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1556,8 +1556,8 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
 		vlv_phy_prepare_pll(crtc, dividers->n,
 				    dividers->m1, dividers->m2,
 				    dividers->p1, dividers->p2,
-				    pipe_config->port_clock,
-				    pipe_config->has_dp_encoder);
+				    pipe_config->dpll_hw_state.lpf,
+				    pipe_config->dpll_hw_state.ssc);
 	}
 
 	assert_pipe_disabled(dev_priv, pipe);
@@ -7203,6 +7203,17 @@ static void vlv_compute_dpll(struct intel_crtc *crtc,
 	if (!pipe_config->has_dsi_encoder)
 		pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
 			DPLL_EXT_BUFFER_ENABLE_VLV;
+
+	/* Set HBR and RBR LPF coefficients */
+	if (pipe_config->has_dp_encoder && pipe_config->port_clock != 162000)
+		pipe_config->dpll_hw_state.lpf = 0x00d0000f;
+	else
+		pipe_config->dpll_hw_state.lpf = 0x009f0003;
+
+	if (pipe_config->has_dp_encoder)
+		pipe_config->dpll_hw_state.ssc = true;
+	else
+		pipe_config->dpll_hw_state.ssc = false;
 }
 
 static void chv_compute_dpll(struct intel_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index fcadc92..0e145d7 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -591,7 +591,7 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
 
 void vlv_phy_prepare_pll(struct intel_crtc *crtc, u32 bestn,
 			 u32 bestm1, u32 bestm2, u32 bestp1, u32 bestp2,
-			 int port_clock, bool dp)
+			 u32 lpf, bool use_ssc_source)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int pipe = crtc->pipe;
@@ -634,15 +634,9 @@ void vlv_phy_prepare_pll(struct intel_crtc *crtc, u32 bestn,
 	mdiv |= DPIO_ENABLE_CALIBRATION;
 	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
 
-	/* Set HBR and RBR LPF coefficients */
-	if (port_clock == 162000 || !dp)
-		vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
-				 0x009f0003);
-	else
-		vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
-				 0x00d0000f);
+	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), lpf);
 
-	if (dp) {
+	if (use_ssc_source) {
 		/* Use SSC source */
 		if (pipe == PIPE_A)
 			vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index 5d086f5..a60576a 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -104,6 +104,10 @@ struct intel_dpll_hw_state {
 	uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
 		 pcsdw12;
 
+	/* vlv */
+	u32 lpf;
+	bool ssc;
+
 	struct dpll dividers;
 };
 
-- 
2.5.5



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