[PATCH 16/18] read lpf and ssc dpll hw state parameters in VLV

Ander Conselvan de Oliveira ander.conselvan.de.oliveira at intel.com
Fri May 13 09:05:02 UTC 2016


---
 drivers/gpu/drm/i915/i915_drv.h       |  2 ++
 drivers/gpu/drm/i915/i915_reg.h       |  2 +-
 drivers/gpu/drm/i915/intel_dpio_phy.c | 29 +++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dpll_mgr.c |  5 ++++-
 4 files changed, 36 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 69d87ed..8c4f574 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3646,6 +3646,8 @@ void vlv_phy_prepare_pll(struct drm_i915_private *dev_priv,
 			 enum pipe pipe, u32 bestn,
 			 u32 bestm1, u32 bestm2, u32 bestp1, u32 bestp2,
 			 u32 lpf, bool use_ssc_source);
+u32 vlv_phy_read_lpf_coef(struct drm_i915_private *dev_priv, enum pipe pipe);
+bool vlv_phy_read_ssc(struct drm_i915_private *dev_priv, enum pipe pipe);
 void vlv_phy_read_dividers(struct drm_i915_private *dev_priv,
 			   enum pipe pipe, struct intel_dpll *clock);
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 54ce0b1..c8259c1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -948,7 +948,7 @@ enum skl_disp_power_wells {
 #define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
 #define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
 #define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
-#define   DPIO_PLL_REFCLK_SEL_MASK	3
+#define   DPIO_PLL_REFCLK_SEL_MASK	(3 << DPIO_PLL_REFCLK_SEL_SHIFT)
 #define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
 #define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
 #define _VLV_PLL_DW5_CH1		0x8034
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 1fb7f24..851fe38 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -702,6 +702,35 @@ void vlv_phy_prepare_pll(struct drm_i915_private *dev_priv, enum pipe pipe,
 	mutex_unlock(&dev_priv->sb_lock);
 }
 
+bool vlv_phy_read_ssc(struct drm_i915_private *dev_priv, enum pipe pipe)
+{
+	u32 val, refclk_sel;
+
+	mutex_lock(&dev_priv->sb_lock);
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW5(pipe));
+	mutex_unlock(&dev_priv->sb_lock);
+
+	refclk_sel = (val & DPIO_PLL_REFCLK_SEL_MASK) >>
+		DPIO_PLL_REFCLK_SEL_SHIFT;
+
+	if ((pipe == PIPE_A && refclk_sel == 0) ||
+	    (pipe == PIPE_B && refclk_sel == 3))
+		return true;
+	else
+		return false;
+}
+
+u32 vlv_phy_read_lpf_coef(struct drm_i915_private *dev_priv, enum pipe pipe)
+{
+	u32 val;
+
+	mutex_lock(&dev_priv->sb_lock);
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW10(pipe));
+	mutex_unlock(&dev_priv->sb_lock);
+
+	return val;
+}
+
 void vlv_phy_read_dividers(struct drm_i915_private *dev_priv,
 			   enum pipe pipe, struct intel_dpll *clock)
 {
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index b64b5ad..c8b29ed 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1811,8 +1811,11 @@ static bool vlv_pll_get_hw_state(struct drm_i915_private *dev_priv,
 
 	hw_state->dpll = I915_READ(DPLL(pipe)) & ~read_only_bits;
 
-	if (hw_state->dpll & DPLL_VCO_ENABLE)
+	if (hw_state->dpll & DPLL_VCO_ENABLE) {
 		vlv_phy_read_dividers(dev_priv, pipe, &hw_state->dividers);
+		hw_state->ssc = vlv_phy_read_ssc(dev_priv, pipe);
+		hw_state->lpf = vlv_phy_read_lpf_coef(dev_priv, pipe);
+	}
 
 	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
 
-- 
2.5.5



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