[PATCH 05/18] drm/i915: Enable VLV/CHV pixel multiplier in crtc_enable
Ander Conselvan de Oliveira
ander.conselvan.de.oliveira at intel.com
Fri May 13 12:49:41 UTC 2016
The value of the DPLL_MD register is set in every modeset, even when
using DSI, in which case the pipe DPLL is not used. So consider that as
pipe parameters instead of a DPLL one. This will also make it easier to
include VLV/CHV plls in the shared dpll code.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira at intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 64 +++++++++++++++++++-----------------
1 file changed, 33 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 975f135..2a71b08 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1563,9 +1563,6 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
_vlv_enable_pll(crtc, pipe_config);
-
- I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
- POSTING_READ(DPLL_MD(pipe));
}
@@ -1624,27 +1621,6 @@ static void chv_enable_pll(struct intel_crtc *crtc,
if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
_chv_enable_pll(crtc, pipe_config);
- if (pipe != PIPE_A) {
- /*
- * WaPixelRepeatModeFixForC0:chv
- *
- * DPLLCMD is AWOL. Use chicken bits to propagate
- * the value from DPLLBMD to either pipe B or C.
- */
- I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
- I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
- I915_WRITE(CBR4_VLV, 0);
- dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
-
- /*
- * DPLLB VGA mode also seems to cause problems.
- * We should always have it disabled.
- */
- WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
- } else {
- I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
- POSTING_READ(DPLL_MD(pipe));
- }
}
static int intel_num_dvo_pipes(struct drm_device *dev)
@@ -6074,6 +6050,37 @@ static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
}
+static void vlv_crtc_set_pixel_multiplier(struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+
+ u32 dpll_md = (crtc->config->pixel_multiplier - 1) <<
+ DPLL_MD_UDI_MULTIPLIER_SHIFT;
+
+ if (IS_CHERRYVIEW(dev_priv) && pipe != PIPE_A) {
+ /*
+ * WaPixelRepeatModeFixForC0:chv
+ *
+ * DPLLCMD is AWOL. Use chicken bits to propagate
+ * the value from DPLLBMD to either pipe B or C.
+ */
+ I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
+ I915_WRITE(DPLL_MD(PIPE_B), dpll_md);
+ I915_WRITE(CBR4_VLV, 0);
+ dev_priv->chv_dpll_md[pipe] = dpll_md;
+
+ /*
+ * DPLLB VGA mode also seems to cause problems.
+ * We should always have it disabled.
+ */
+ WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
+ } else {
+ I915_WRITE(DPLL_MD(pipe), dpll_md);
+ POSTING_READ(DPLL_MD(pipe));
+ }
+}
+
static void valleyview_crtc_enable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
@@ -6115,6 +6122,8 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
else
vlv_enable_pll(intel_crtc, intel_crtc->config);
+ vlv_crtc_set_pixel_multiplier(intel_crtc);
+
for_each_encoder_on_crtc(dev, crtc, encoder)
if (encoder->pre_enable)
encoder->pre_enable(encoder);
@@ -7184,9 +7193,6 @@ static void vlv_compute_dpll(struct intel_crtc *crtc,
if (!pipe_config->has_dsi_encoder)
pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
DPLL_EXT_BUFFER_ENABLE_VLV;
-
- pipe_config->dpll_hw_state.dpll_md =
- (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
}
static void chv_compute_dpll(struct intel_crtc *crtc,
@@ -7200,9 +7206,6 @@ static void chv_compute_dpll(struct intel_crtc *crtc,
/* DPLL not used with DSI, but still need the rest set up */
if (!pipe_config->has_dsi_encoder)
pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
-
- pipe_config->dpll_hw_state.dpll_md =
- (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
}
/**
@@ -7227,7 +7230,6 @@ int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
return -ENOMEM;
pipe_config->base.crtc = &crtc->base;
- pipe_config->pixel_multiplier = 1;
pipe_config->dpll = *dpll;
if (IS_CHERRYVIEW(dev)) {
--
2.5.5
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