[PATCH 11/17] drm/i915: Make POWER_DOMAIN_PLLS enable disp2d in VLV/CHV

[Ander Conselvan de Oliveira]

Reads of DPLL(pipe) return bogus values if disp2d is disabled. Once
VLV/CHV plls become part of the shared dpll infrastructure, the code
will need to check for POWER_DOMAIN_PLLS before attempting a hardware
state readout. So make sure that if that power domain is enabled then
the DPLL register can be read.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira at intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index b69b935..c181691 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1666,6 +1666,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	BIT(POWER_DOMAIN_AUX_B) |		\
 	BIT(POWER_DOMAIN_AUX_C) |		\
 	BIT(POWER_DOMAIN_GMBUS) |		\
+	BIT(POWER_DOMAIN_PLLS) |		\
 	BIT(POWER_DOMAIN_INIT))
 
 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (		\
@@ -1716,6 +1717,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	BIT(POWER_DOMAIN_AUX_C) |		\
 	BIT(POWER_DOMAIN_AUX_D) |		\
 	BIT(POWER_DOMAIN_GMBUS) |		\
+	BIT(POWER_DOMAIN_PLLS) |		\
 	BIT(POWER_DOMAIN_INIT))
 
 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (		\
-- 
2.5.5