[PATCH] trybot gen8 wm
Maarten Lankhorst
maarten.lankhorst at linux.intel.com
Mon May 23 09:54:19 UTC 2016
---
drivers/gpu/drm/i915/intel_display.c | 6 -
drivers/gpu/drm/i915/intel_drv.h | 54 +++-----
drivers/gpu/drm/i915/intel_pm.c | 262 +++++++++++++++++++++--------------
3 files changed, 177 insertions(+), 145 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 94d28c795e22..da1d2cac9f19 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4598,8 +4598,6 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
intel_frontbuffer_flip(dev, pipe_config->fb_bits);
- crtc->wm.cxsr_allowed = true;
-
if (pipe_config->update_wm_post && pipe_config->base.active)
intel_update_watermarks(&crtc->base);
@@ -4645,8 +4643,6 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
}
if (pipe_config->disable_cxsr) {
- crtc->wm.cxsr_allowed = false;
-
/*
* Vblank time updates from the shadow to live plane control register
* are blocked if the memory self-refresh mode is active at that
@@ -14331,8 +14327,6 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
intel_crtc->cursor_cntl = ~0;
intel_crtc->cursor_size = ~0;
- intel_crtc->wm.cxsr_allowed = true;
-
BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3536292babe0..cd035fb23714 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -417,6 +417,16 @@ struct skl_pipe_wm {
uint32_t linetime;
};
+struct vlv_wm_state {
+ struct vlv_pipe_wm wm[3];
+ struct vlv_sr_wm sr[3];
+ uint16_t fifo_size[I915_MAX_PLANES];
+ uint8_t num_active_planes;
+ uint8_t num_levels;
+ uint8_t level;
+ bool cxsr;
+};
+
struct intel_crtc_wm_state {
union {
struct {
@@ -437,6 +447,12 @@ struct intel_crtc_wm_state {
} ilk;
struct {
+ /* Intermediate watermarks, calculated without CxSR. */
+ struct vlv_wm_state intermediate;
+ struct vlv_wm_state optimal;
+ } vlv;
+
+ struct {
/* gen9+ only needs 1-step wm programming */
struct skl_pipe_wm optimal;
@@ -618,15 +634,6 @@ struct intel_crtc_state {
uint32_t gamma_mode;
};
-struct vlv_wm_state {
- struct vlv_pipe_wm wm[3];
- struct vlv_sr_wm sr[3];
- uint8_t num_active_planes;
- uint8_t num_levels;
- uint8_t level;
- bool cxsr;
-};
-
struct intel_mmio_flip {
struct work_struct work;
struct drm_i915_private *i915;
@@ -681,9 +688,6 @@ struct intel_crtc {
struct intel_pipe_wm ilk;
struct skl_pipe_wm skl;
} active;
-
- /* allow CxSR on this pipe */
- bool cxsr_allowed;
} wm;
int scanline_offset;
@@ -701,25 +705,6 @@ struct intel_crtc {
struct vlv_wm_state wm_state;
};
-struct intel_plane_wm_parameters {
- uint32_t horiz_pixels;
- uint32_t vert_pixels;
- /*
- * For packed pixel formats:
- * bytes_per_pixel - holds bytes per pixel
- * For planar pixel formats:
- * bytes_per_pixel - holds bytes per pixel for uv-plane
- * y_bytes_per_pixel - holds bytes per pixel for y-plane
- */
- uint8_t bytes_per_pixel;
- uint8_t y_bytes_per_pixel;
- bool enabled;
- bool scaled;
- u64 tiling;
- unsigned int rotation;
- uint16_t fifo_size;
-};
-
struct intel_plane {
struct drm_plane base;
int plane;
@@ -728,13 +713,6 @@ struct intel_plane {
int max_downscale;
uint32_t frontbuffer_bit;
- /* Since we need to change the watermarks before/after
- * enabling/disabling the planes, we need to store the parameters here
- * as the other pieces of the struct may not reflect the values we want
- * for the watermark calculations. Currently only Haswell uses this.
- */
- struct intel_plane_wm_parameters wm;
-
/*
* NOTE: Do not place new plane state fields here (e.g., when adding
* new plane properties). New runtime state should now be placed in
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index adb64638f595..87b1296f00f5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -54,6 +54,28 @@
#define INTEL_RC6p_ENABLE (1<<1)
#define INTEL_RC6pp_ENABLE (1<<2)
+/*
+ * Return the index of a plane in the SKL DDB and wm result arrays. Primary
+ * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
+ * other universal planes are in indices 1..n. Note that this may leave unused
+ * indices between the top "sprite" plane and the cursor.
+ */
+static int
+wm_plane_id(const struct intel_plane *plane)
+{
+ switch (plane->base.type) {
+ case DRM_PLANE_TYPE_PRIMARY:
+ return 0;
+ case DRM_PLANE_TYPE_CURSOR:
+ return PLANE_CURSOR;
+ case DRM_PLANE_TYPE_OVERLAY:
+ return plane->plane + 1;
+ default:
+ MISSING_CASE(plane->base.type);
+ return plane->plane;
+ }
+}
+
static void bxt_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -921,7 +943,7 @@ static void vlv_setup_wm_latency(struct drm_device *dev)
}
static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
- struct intel_crtc *crtc,
+ const struct intel_crtc_state *cstate,
const struct intel_plane_state *state,
int level)
{
@@ -935,9 +957,9 @@ static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
return 0;
cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
- clock = crtc->config->base.adjusted_mode.crtc_clock;
- htotal = crtc->config->base.adjusted_mode.crtc_htotal;
- width = crtc->config->pipe_src_w;
+ clock = cstate->base.adjusted_mode.crtc_clock;
+ htotal = cstate->base.adjusted_mode.crtc_htotal;
+ width = cstate->pipe_src_w;
if (WARN_ON(htotal == 0))
htotal = 1;
@@ -957,76 +979,79 @@ static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
return min_t(int, wm, USHRT_MAX);
}
-static void vlv_compute_fifo(struct intel_crtc *crtc)
+static void vlv_compute_fifo(struct intel_crtc_state *cstate,
+ struct vlv_wm_state *wm_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
struct drm_device *dev = crtc->base.dev;
- struct vlv_wm_state *wm_state = &crtc->wm_state;
struct intel_plane *plane;
unsigned int total_rate = 0;
const int fifo_size = 512 - 1;
int fifo_extra, fifo_left = fifo_size;
+ int rate[I915_MAX_PLANES] = {};
+ int i;
- for_each_intel_plane_on_crtc(dev, crtc, plane) {
+ for_each_intel_plane_mask(dev, plane, cstate->base.plane_mask) {
struct intel_plane_state *state =
- to_intel_plane_state(plane->base.state);
+ intel_atomic_get_existing_plane_state(cstate->base.state,
+ plane);
+
+ if (!state)
+ state = to_intel_plane_state(plane->base.state);
if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
continue;
if (state->visible) {
wm_state->num_active_planes++;
- total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
+ rate[wm_plane_id(plane)] = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
+ total_rate += rate[wm_plane_id(plane)];
}
}
- for_each_intel_plane_on_crtc(dev, crtc, plane) {
- struct intel_plane_state *state =
- to_intel_plane_state(plane->base.state);
- unsigned int rate;
-
- if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
- plane->wm.fifo_size = 63;
+ for (i = 0; i < I915_MAX_PLANES; i++) {
+ if (i == PLANE_CURSOR) {
+ wm_state->fifo_size[i] = 63;
continue;
}
- if (!state->visible) {
- plane->wm.fifo_size = 0;
+ if (!rate[i]) {
+ wm_state->fifo_size[i] = 0;
continue;
}
- rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
- plane->wm.fifo_size = fifo_size * rate / total_rate;
- fifo_left -= plane->wm.fifo_size;
+ wm_state->fifo_size[i] = fifo_size * rate[i] / total_rate;
+ fifo_left -= wm_state->fifo_size[i];
}
fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
/* spread the remainder evenly */
- for_each_intel_plane_on_crtc(dev, crtc, plane) {
+ for (i = 0; i < I915_MAX_PLANES; i++) {
int plane_extra;
if (fifo_left == 0)
break;
- if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
+ if (i == PLANE_CURSOR)
continue;
/* give it all to the first plane if none are active */
- if (plane->wm.fifo_size == 0 &&
+ if (!wm_state->fifo_size[i] &&
wm_state->num_active_planes)
continue;
plane_extra = min(fifo_extra, fifo_left);
- plane->wm.fifo_size += plane_extra;
+ wm_state->fifo_size[i] += plane_extra;
fifo_left -= plane_extra;
}
WARN_ON(fifo_left != 0);
}
-static void vlv_invert_wms(struct intel_crtc *crtc)
+static void vlv_invert_wms(struct intel_crtc *crtc,
+ struct vlv_wm_state *wm_state)
{
- struct vlv_wm_state *wm_state = &crtc->wm_state;
int level;
for (level = 0; level < wm_state->num_levels; level++) {
@@ -1038,19 +1063,21 @@ static void vlv_invert_wms(struct intel_crtc *crtc)
wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
for_each_intel_plane_on_crtc(dev, crtc, plane) {
+ int i = wm_plane_id(plane);
+
switch (plane->base.type) {
int sprite;
case DRM_PLANE_TYPE_CURSOR:
- wm_state->wm[level].cursor = plane->wm.fifo_size -
+ wm_state->wm[level].cursor = wm_state->fifo_size[i] -
wm_state->wm[level].cursor;
break;
case DRM_PLANE_TYPE_PRIMARY:
- wm_state->wm[level].primary = plane->wm.fifo_size -
+ wm_state->wm[level].primary = wm_state->fifo_size[i] -
wm_state->wm[level].primary;
break;
case DRM_PLANE_TYPE_OVERLAY:
sprite = plane->plane;
- wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
+ wm_state->wm[level].sprite[sprite] = wm_state->fifo_size[i] -
wm_state->wm[level].sprite[sprite];
break;
}
@@ -1058,22 +1085,21 @@ static void vlv_invert_wms(struct intel_crtc *crtc)
}
}
-static void vlv_compute_wm(struct intel_crtc *crtc)
+static int vlv_compute_pipe_wm(struct intel_crtc_state *cstate)
{
+ struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
struct drm_device *dev = crtc->base.dev;
- struct vlv_wm_state *wm_state = &crtc->wm_state;
+ struct vlv_wm_state *wm_state = &cstate->wm.vlv.optimal;
struct intel_plane *plane;
int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
int level;
memset(wm_state, 0, sizeof(*wm_state));
- wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
+ wm_state->cxsr = crtc->pipe != PIPE_C;
wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
- wm_state->num_active_planes = 0;
-
- vlv_compute_fifo(crtc);
+ vlv_compute_fifo(cstate, wm_state);
if (wm_state->num_active_planes != 1)
wm_state->cxsr = false;
@@ -1085,23 +1111,38 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
}
}
- for_each_intel_plane_on_crtc(dev, crtc, plane) {
+ for_each_intel_plane_mask(dev, plane, cstate->base.plane_mask) {
struct intel_plane_state *state =
- to_intel_plane_state(plane->base.state);
+ intel_atomic_get_existing_plane_state(cstate->base.state,
+ plane);
+
+ /*
+ * Because we hold the crtc mutex planes that are part of
+ * plane_mask cannot be removed from this crtc while we hold
+ * the lock. This will allow us to inspect plane->state
+ * when the plane's not part of the state without the state
+ * being updated.
+ */
+ if (!state)
+ state = to_intel_plane_state(plane->base.state);
if (!state->visible)
continue;
/* normal watermarks */
for (level = 0; level < wm_state->num_levels; level++) {
- int wm = vlv_compute_wm_level(plane, crtc, state, level);
+ int wm = vlv_compute_wm_level(plane, cstate, state, level);
int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
- /* hack */
- if (WARN_ON(level == 0 && wm > max_wm))
- wm = max_wm;
+ if (level == 0 && wm > max_wm) {
+ DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
+ DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u\n",
+ to_intel_crtc(cstate->base.crtc)->pipe,
+ drm_plane_index(&plane->base), wm, max_wm);
+ return -EINVAL;
+ }
- if (wm > plane->wm.fifo_size)
+ if (wm > wm_state->fifo_size[wm_plane_id(plane)])
break;
switch (plane->base.type) {
@@ -1154,7 +1195,9 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
}
- vlv_invert_wms(crtc);
+ vlv_invert_wms(crtc, wm_state);
+
+ return 0;
}
#define VLV_FIFO(plane, value) \
@@ -1164,24 +1207,18 @@ static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_plane *plane;
int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
+ const struct vlv_wm_state *wm_state = &crtc->wm_state;
- for_each_intel_plane_on_crtc(dev, crtc, plane) {
- if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
- WARN_ON(plane->wm.fifo_size != 63);
- continue;
- }
+ WARN_ON(wm_state->fifo_size[PLANE_CURSOR] != 63);
- if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
- sprite0_start = plane->wm.fifo_size;
- else if (plane->plane == 0)
- sprite1_start = sprite0_start + plane->wm.fifo_size;
- else
- fifo_size = sprite1_start + plane->wm.fifo_size;
- }
+ sprite0_start = wm_state->fifo_size[0];
+ sprite1_start = sprite0_start + wm_state->fifo_size[1];
+ fifo_size = sprite1_start + wm_state->fifo_size[2];
- WARN_ON(fifo_size != 512 - 1);
+ WARN(fifo_size != 512 - 1, "Pipe %c FIFO split %d / %d / %d\n",
+ pipe_name(crtc->pipe), sprite0_start,
+ sprite1_start, fifo_size);
DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
pipe_name(crtc->pipe), sprite0_start,
@@ -1293,6 +1330,23 @@ static void vlv_merge_wm(struct drm_device *dev,
}
}
+static int vlv_compute_intermediate_wm(struct drm_device *dev,
+ struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *newstate)
+{
+ struct vlv_wm_state *wm_state = &newstate->wm.vlv.intermediate;
+ *wm_state = newstate->wm.vlv.optimal;
+
+ if (!newstate->disable_cxsr || !newstate->wm.vlv.optimal.cxsr)
+ return 0;
+
+ wm_state->cxsr = false;
+ memset(wm_state->sr, 0, sizeof(wm_state->sr));
+ newstate->wm.need_postvbl_update = true;
+
+ return 0;
+}
+
static void vlv_update_wm(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
@@ -1301,7 +1355,6 @@ static void vlv_update_wm(struct drm_crtc *crtc)
enum pipe pipe = intel_crtc->pipe;
struct vlv_wm_values wm = {};
- vlv_compute_wm(intel_crtc);
vlv_merge_wm(dev, &wm);
if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
@@ -1346,6 +1399,28 @@ static void vlv_update_wm(struct drm_crtc *crtc)
dev_priv->wm.vlv = wm;
}
+static void vlv_initial_watermarks(struct intel_crtc_state *cstate)
+{
+ struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+ struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
+
+ mutex_lock(&dev_priv->wm.wm_mutex);
+ crtc->wm_state = cstate->wm.vlv.intermediate;
+ vlv_update_wm(&crtc->base);
+ mutex_unlock(&dev_priv->wm.wm_mutex);
+}
+
+static void vlv_optimize_watermarks(struct intel_crtc_state *cstate)
+{
+ struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+ struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
+
+ mutex_lock(&dev_priv->wm.wm_mutex);
+ crtc->wm_state = cstate->wm.vlv.optimal;
+ vlv_update_wm(&crtc->base);
+ mutex_unlock(&dev_priv->wm.wm_mutex);
+}
+
#define single_plane_enabled(mask) is_power_of_2(mask)
static void g4x_update_wm(struct drm_crtc *crtc)
@@ -2824,28 +2899,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
#define SKL_DDB_SIZE 896 /* in blocks */
#define BXT_DDB_SIZE 512
-/*
- * Return the index of a plane in the SKL DDB and wm result arrays. Primary
- * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
- * other universal planes are in indices 1..n. Note that this may leave unused
- * indices between the top "sprite" plane and the cursor.
- */
-static int
-skl_wm_plane_id(const struct intel_plane *plane)
-{
- switch (plane->base.type) {
- case DRM_PLANE_TYPE_PRIMARY:
- return 0;
- case DRM_PLANE_TYPE_CURSOR:
- return PLANE_CURSOR;
- case DRM_PLANE_TYPE_OVERLAY:
- return plane->plane + 1;
- default:
- MISSING_CASE(plane->base.type);
- return plane->plane;
- }
-}
-
static void
skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
const struct intel_crtc_state *cstate,
@@ -3007,7 +3060,7 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
/* Calculate and cache data rate for each plane */
for_each_plane_in_state(state, plane, pstate, i) {
- id = skl_wm_plane_id(to_intel_plane(plane));
+ id = wm_plane_id(to_intel_plane(plane));
intel_plane = to_intel_plane(plane);
if (intel_plane->pipe != intel_crtc->pipe)
@@ -3026,7 +3079,7 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
/* Calculate CRTC's total data rate from cached values */
for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
- int id = skl_wm_plane_id(intel_plane);
+ int id = wm_plane_id(intel_plane);
/* packed/uv */
total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
@@ -3084,7 +3137,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
/* 1. Allocate the mininum required blocks for each active plane */
for_each_plane_in_state(state, plane, pstate, i) {
intel_plane = to_intel_plane(plane);
- id = skl_wm_plane_id(intel_plane);
+ id = wm_plane_id(intel_plane);
if (intel_plane->pipe != pipe)
continue;
@@ -3126,7 +3179,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
unsigned int data_rate, y_data_rate;
uint16_t plane_blocks, y_plane_blocks = 0;
- int id = skl_wm_plane_id(intel_plane);
+ int id = wm_plane_id(intel_plane);
data_rate = cstate->wm.skl.plane_data_rate[id];
@@ -3317,7 +3370,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
to_intel_crtc(cstate->base.crtc)->pipe,
- skl_wm_plane_id(to_intel_plane(pstate->plane)),
+ wm_plane_id(to_intel_plane(pstate->plane)),
res_blocks, ddb_allocation, res_lines);
return -EINVAL;
@@ -3355,7 +3408,7 @@ skl_compute_wm_level(const struct drm_i915_private *dev_priv,
memset(result, 0, sizeof(*result));
for_each_intel_plane_mask(dev, intel_plane, cstate->base.plane_mask) {
- int i = skl_wm_plane_id(intel_plane);
+ int i = wm_plane_id(intel_plane);
plane = &intel_plane->base;
intel_pstate = NULL;
@@ -3424,7 +3477,7 @@ static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
/* Until we know more, just disable transition WMs */
for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
- int i = skl_wm_plane_id(intel_plane);
+ int i = wm_plane_id(intel_plane);
trans_wm->plane_en[i] = false;
}
@@ -4064,7 +4117,7 @@ void skl_wm_get_hw_state(struct drm_device *dev)
for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
const struct drm_plane_state *pstate =
intel_plane->base.state;
- int id = skl_wm_plane_id(intel_plane);
+ int id = wm_plane_id(intel_plane);
cstate->wm.skl.plane_data_rate[id] =
skl_plane_relative_data_rate(cstate, pstate, 0);
@@ -4211,6 +4264,7 @@ void vlv_wm_get_hw_state(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct vlv_wm_values *wm = &dev_priv->wm.vlv;
+ struct intel_crtc *crtc;
struct intel_plane *plane;
enum pipe pipe;
u32 val;
@@ -4218,17 +4272,19 @@ void vlv_wm_get_hw_state(struct drm_device *dev)
vlv_read_wm_values(dev_priv, wm);
for_each_intel_plane(dev, plane) {
+ struct vlv_wm_state *wm_state;
+ int i = wm_plane_id(plane);
+
+ crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, plane->pipe));
+ wm_state = &crtc->wm_state;
+
switch (plane->base.type) {
- int sprite;
case DRM_PLANE_TYPE_CURSOR:
- plane->wm.fifo_size = 63;
+ wm_state->fifo_size[i] = 63;
break;
case DRM_PLANE_TYPE_PRIMARY:
- plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
- break;
case DRM_PLANE_TYPE_OVERLAY:
- sprite = plane->plane;
- plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
+ wm_state->fifo_size[i] = vlv_get_fifo_size(dev, plane->pipe, i);
break;
}
}
@@ -4270,10 +4326,14 @@ void vlv_wm_get_hw_state(struct drm_device *dev)
mutex_unlock(&dev_priv->rps.hw_lock);
}
- for_each_pipe(dev_priv, pipe)
+ for_each_intel_crtc(dev, crtc) {
+ pipe = crtc->pipe;
+ to_intel_crtc_state(crtc->base.state)->wm.vlv.optimal = crtc->wm_state;
+
DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
+ }
DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
@@ -7377,12 +7437,12 @@ void intel_init_pm(struct drm_device *dev)
DRM_DEBUG_KMS("Failed to read display plane latency. "
"Disable CxSR\n");
}
- } else if (IS_CHERRYVIEW(dev)) {
- vlv_setup_wm_latency(dev);
- dev_priv->display.update_wm = vlv_update_wm;
- } else if (IS_VALLEYVIEW(dev)) {
+ } else if (IS_CHERRYVIEW(dev) || IS_VALLEYVIEW(dev)) {
vlv_setup_wm_latency(dev);
- dev_priv->display.update_wm = vlv_update_wm;
+ dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;
+ dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;
+ dev_priv->display.initial_watermarks = vlv_initial_watermarks;
+ dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;
} else if (IS_PINEVIEW(dev)) {
if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
dev_priv->is_ddr3,
--
2.5.5
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