[PATCH 05/15] drm/i915: u16 is wide enough for latency_ns

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 96d0c57c816c..4b6bb2709c38 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -372,7 +372,7 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
  * A value of 5us seems to be a good balance; safe for very low end
  * platforms but not overly aggressive on lower latency configs.
  */
-static const int pessimal_latency_ns = 5000;
+static const u16 pessimal_latency_ns = 5000;
 
 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 	((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
@@ -585,7 +585,7 @@ static const struct intel_watermark_params i845_wm_info = {
 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 					const struct intel_watermark_params *wm,
 					int fifo_size, int cpp,
-					unsigned long latency_ns)
+					u16 latency_ns)
 {
 	long entries_required, wm_size;
 
@@ -709,7 +709,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc)
 static bool g4x_compute_wm0(struct drm_device *dev,
 			    int plane,
 			    const struct intel_watermark_params *display,
-			    int display_latency_ns,
+			    u16 display_latency_ns,
 			    const struct intel_watermark_params *cursor,
 			    int cursor_latency_ns,
 			    int *plane_wm,
-- 
2.7.4