[PATCH 15/15] drm/i915: Tidy types in i9xx_update_wm

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7fc531641ea5..3bb02b0be531 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1518,9 +1518,10 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 	struct drm_device *dev = unused_crtc->dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	const struct intel_watermark_params *wm_info;
-	uint32_t fwater_lo;
-	uint32_t fwater_hi;
-	int cwm, srwm = 1;
+	u32 fwater_lo;
+	u32 fwater_hi;
+	u8 cwm;
+	int srwm = 1;
 	u16 fifo_size;
 	u16 planea_wm, planeb_wm;
 	struct drm_crtc *crtc, *enabled = NULL;
@@ -1599,14 +1600,13 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 	/* Calc sr entries for one plane configs */
 	if (HAS_FW_BLC(dev) && enabled) {
 		/* self-refresh has much higher latency */
-		static const int sr_latency_ns = 6000;
+		static const u16 sr_latency_ns = 6000;
 		const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
 		int clock = adjusted_mode->crtc_clock;
 		int htotal = adjusted_mode->crtc_htotal;
 		int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
 		int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
-		unsigned long line_time_us;
-		int entries;
+		unsigned int line_time_us, entries;
 
 		if (IS_I915GM(dev) || IS_I945GM(dev))
 			cpp = 4;
@@ -1617,7 +1617,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 		entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
 			cpp * hdisplay;
 		entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
-		DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
+		DRM_DEBUG_KMS("self-refresh entries: %u\n", entries);
 		srwm = wm_info->fifo_size - entries;
 		if (srwm < 0)
 			srwm = 1;
@@ -1629,7 +1629,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 			I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
 	}
 
-	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
+	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %u, B: %u, C: %u, SR %d\n",
 		      planea_wm, planeb_wm, cwm, srwm);
 
 	fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
-- 
2.7.4