[PATCH v5 06/23] drm/i915/slpc: Use intel_slpc_* functions if supported

Sagar Arun Kamble sagar.a.kamble at intel.com
Sat Oct 22 08:17:03 UTC 2016


From: Tom O'Rourke <Tom.O'Rourke at intel.com>

On platforms with SLPC support: call intel_slpc_*()
functions from corresponding intel_*_gt_powersave()
functions; and do not use rps functions.

v1: Return void instead of ignored error code (Paulo)
    enable/disable RC6 in SLPC flows (Sagar)
    replace HAS_SLPC() use with intel_slpc_enabled()
	or intel_slpc_active() (Paulo)
    Fix for renaming gen9_disable_rps to gen9_disable_rc6 in
    "drm/i915/bxt: Explicitly clear the Turbo control register"
    Defer RC6 and SLPC enabling to intel_gen6_powersave_work. (Sagar)
    Performance drop with SLPC was happening as ring frequency table
    was not programmed when SLPC was enabled. This patch programs ring
    frequency table with SLPC. Initial reset of SLPC is based on kernel
    parameter as planning to add slpc state in intel_slpc_active. Cleanup
    is also based on kernel parameter as SLPC gets disabled in
    disable/suspend.(Sagar)

v2: Usage of INTEL_GEN instead of INTEL_INFO->gen (David)
    Checkpatch update.

v3: Rebase

v4: Removed reset functions to comply with *_gt_powersave routines.
    (Sagar)

v5: Removed intel_slpc_active. Relying on slpc.active for control flows
    that are based on SLPC active status in GuC. State setup/cleanup needed
    for SLPC is handled using kernel parameter i915.enable_slpc.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke at intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
---
 drivers/gpu/drm/i915/Makefile     |  3 +-
 drivers/gpu/drm/i915/i915_drv.c   |  6 ++++
 drivers/gpu/drm/i915/i915_gem.c   | 10 +++++--
 drivers/gpu/drm/i915/intel_guc.h  |  3 ++
 drivers/gpu/drm/i915/intel_pm.c   | 60 +++++++++++++++++++++++++++++----------
 drivers/gpu/drm/i915/intel_slpc.c | 46 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h | 38 +++++++++++++++++++++++++
 7 files changed, 147 insertions(+), 19 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6123400..2bae39e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -52,7 +52,8 @@ i915-y += i915_cmd_parser.o \
 
 # general-purpose microcontroller (GuC) support
 i915-y += intel_guc_loader.o \
-	  i915_guc_submission.o
+	  i915_guc_submission.o \
+	  intel_slpc.o
 
 # autogenerated null render state
 i915-y += intel_renderstate_gen6.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d4648b6..ab31466 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1687,6 +1687,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
 		hsw_disable_pc8(dev_priv);
 	}
 
+	dev_priv->guc.slpc.active = false;
+
 	intel_uncore_sanitize(dev_priv);
 
 	if (IS_BROXTON(dev_priv) ||
@@ -1800,6 +1802,10 @@ void i915_reset(struct drm_i915_private *dev_priv)
 		goto error;
 	}
 
+	/* Enabling SLPC post GuC reinitialization */
+	if (i915.enable_slpc)
+		intel_enable_gt_powersave(dev_priv);
+
 wakeup:
 	wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS);
 	return;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8ed8e24..36f2e9a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2633,11 +2633,15 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
 
 	i915_gem_restore_fences(&dev_priv->drm);
 
+	dev_priv->guc.slpc.active = false;
+
 	if (dev_priv->gt.awake) {
 		intel_sanitize_gt_powersave(dev_priv);
-		intel_enable_gt_powersave(dev_priv);
-		if (INTEL_GEN(dev_priv) >= 6)
-			gen6_rps_busy(dev_priv);
+		if (!i915.enable_slpc) {
+			intel_enable_gt_powersave(dev_priv);
+			if (INTEL_GEN(dev_priv) >= 6)
+				gen6_rps_busy(dev_priv);
+		}
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index baeb7ad..04b301d 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -27,6 +27,7 @@
 #include "intel_guc_fwif.h"
 #include "i915_guc_reg.h"
 #include "intel_ringbuffer.h"
+#include "intel_slpc.h"
 
 struct drm_i915_gem_request;
 
@@ -146,6 +147,8 @@ struct intel_guc {
 
 	uint64_t submissions[I915_NUM_ENGINES];
 	uint32_t last_seqno[I915_NUM_ENGINES];
+
+	struct intel_slpc slpc;
 };
 
 /* intel_guc_loader.c */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index df56435..50f0746 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5056,7 +5056,8 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
 	 * our rpm wakeref. And then disable the interrupts to stop any
 	 * futher RPS reclocking whilst we are asleep.
 	 */
-	gen6_disable_rps_interrupts(dev_priv);
+	if (!i915.enable_slpc)
+		gen6_disable_rps_interrupts(dev_priv);
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (dev_priv->rps.enabled) {
@@ -6711,6 +6712,9 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 	/* Finally allow us to boost to max by default */
 	dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
 
+	if (i915.enable_slpc)
+		intel_slpc_init(dev_priv);
+
 	mutex_unlock(&dev_priv->rps.hw_lock);
 	mutex_unlock(&dev_priv->drm.struct_mutex);
 
@@ -6719,7 +6723,9 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 
 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (IS_VALLEYVIEW(dev_priv))
+	if (i915.enable_slpc)
+		intel_slpc_cleanup(dev_priv);
+	else if (IS_VALLEYVIEW(dev_priv))
 		valleyview_cleanup_gt_powersave(dev_priv);
 
 	if (!i915.enable_rc6)
@@ -6739,18 +6745,24 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
 	if (INTEL_GEN(dev_priv) < 6)
 		return;
 
-	if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
+	if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work)) {
+		if (dev_priv->guc.slpc.active)
+			intel_slpc_suspend(dev_priv);
 		intel_runtime_pm_put(dev_priv);
+	}
 
 	/* gen6_rps_idle() will be called later to disable interrupts */
 }
 
 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	dev_priv->rps.enabled = true; /* force disabling */
+	if (!i915.enable_slpc)
+		dev_priv->rps.enabled = true; /* force disabling */
+
 	intel_disable_gt_powersave(dev_priv);
 
-	gen6_reset_rps_interrupts(dev_priv);
+	if (!i915.enable_slpc)
+		gen6_reset_rps_interrupts(dev_priv);
 }
 
 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
@@ -6762,11 +6774,19 @@ void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 
 	if (INTEL_GEN(dev_priv) >= 9) {
 		gen9_disable_rc6(dev_priv);
-		if (!READ_ONCE(dev_priv->rps.enabled)) {
-			mutex_unlock(&dev_priv->rps.hw_lock);
-			return;
+		if (i915.enable_slpc) {
+			if (!READ_ONCE(dev_priv->guc.slpc.active)) {
+				mutex_unlock(&dev_priv->rps.hw_lock);
+				return;
+			}
+			intel_slpc_disable(dev_priv);
+		} else {
+			if (!READ_ONCE(dev_priv->rps.enabled)) {
+				mutex_unlock(&dev_priv->rps.hw_lock);
+				return;
+			}
+			gen9_disable_rps(dev_priv);
 		}
-		gen9_disable_rps(dev_priv);
 	} else if (IS_CHERRYVIEW(dev_priv)) {
 		cherryview_disable_rps(dev_priv);
 	} else if (IS_VALLEYVIEW(dev_priv)) {
@@ -6800,11 +6820,19 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 		valleyview_enable_rps(dev_priv);
 	} else if (INTEL_GEN(dev_priv) >= 9) {
 		gen9_enable_rc6(dev_priv);
-		if (READ_ONCE(dev_priv->rps.enabled)) {
-			mutex_unlock(&dev_priv->rps.hw_lock);
-			return;
+		if (i915.enable_slpc) {
+			if (READ_ONCE(dev_priv->guc.slpc.active)) {
+				mutex_unlock(&dev_priv->rps.hw_lock);
+				return;
+			}
+			intel_slpc_enable(dev_priv);
+		} else {
+			if (READ_ONCE(dev_priv->rps.enabled)) {
+				mutex_unlock(&dev_priv->rps.hw_lock);
+				return;
+			}
+			gen9_enable_rps(dev_priv);
 		}
-		gen9_enable_rps(dev_priv);
 		if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 			gen6_update_ring_freq(dev_priv);
 	} else if (IS_BROADWELL(dev_priv)) {
@@ -6834,7 +6862,8 @@ static void __intel_autoenable_gt_powersave(struct work_struct *work)
 	struct intel_engine_cs *rcs;
 	struct drm_i915_gem_request *req;
 
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if ((i915.enable_slpc && READ_ONCE(dev_priv->guc.slpc.active)) ||
+	    (!i915.enable_slpc && READ_ONCE(dev_priv->rps.enabled)))
 		goto out;
 
 	rcs = dev_priv->engine[RCS];
@@ -6864,7 +6893,8 @@ static void __intel_autoenable_gt_powersave(struct work_struct *work)
 
 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if ((i915.enable_slpc && READ_ONCE(dev_priv->guc.slpc.active)) ||
+	    (!i915.enable_slpc && READ_ONCE(dev_priv->rps.enabled)))
 		return;
 
 	if (IS_IRONLAKE_M(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
new file mode 100644
index 0000000..b67f1bc
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#include <linux/firmware.h>
+#include "i915_drv.h"
+#include "intel_guc.h"
+
+void intel_slpc_init(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_suspend(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_disable(struct drm_i915_private *dev_priv)
+{
+}
+
+void intel_slpc_enable(struct drm_i915_private *dev_priv)
+{
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
new file mode 100644
index 0000000..e5acfc8
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#ifndef _INTEL_SLPC_H_
+#define _INTEL_SLPC_H_
+
+struct intel_slpc {
+	bool active;
+};
+
+/* intel_slpc.c */
+void intel_slpc_init(struct drm_i915_private *dev_priv);
+void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
+void intel_slpc_suspend(struct drm_i915_private *dev_priv);
+void intel_slpc_disable(struct drm_i915_private *dev_priv);
+void intel_slpc_enable(struct drm_i915_private *dev_priv);
+
+#endif
-- 
1.9.1



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