[PATCH v5 01/23] drm/i915/gen9: Separate RPS and RC6 handling
Sagar Arun Kamble
sagar.a.kamble at intel.com
Sat Oct 22 08:16:58 UTC 2016
RPS active check in Suspend flow is needed for platforms with RC6 and RPS
enabling/disabling coupled together. RPM suspend depends only on RC6 though.
With this patch for Gen9, RC6 and RPS enabling is separated hence RPS enabled
check is done only for non-Gen9 platforms. Once RC6 and RPS enabling is
separated for other GENs this check can be completely removed.
Moved setting of rps.enabled to platform level functions as there is case
of disabling of RPS in gen9_enable_rps.
v2: Changing parameter to dev_priv for IS_GEN9 and HAS_RUNTIME_PM and line
spacing changes. (David)
and commit message update for checkpatch issues.
v3: Rebase.
v4: Commit message update.
v5: Updated intel_enable_gt_powersave and intel_disable_gt_powersave
routines with separated RPS and RC6 handling and rebase. (Sagar)
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 10 +++++++++-
drivers/gpu/drm/i915/intel_pm.c | 32 ++++++++++++++++++++++++++++----
2 files changed, 37 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 912d534..d4648b6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2293,9 +2293,17 @@ static int intel_runtime_suspend(struct device *kdev)
struct drm_i915_private *dev_priv = to_i915(dev);
int ret;
- if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
+ if (WARN_ON_ONCE(!intel_enable_rc6()))
return -ENODEV;
+ /*
+ * Once RC6 and RPS enabling is separated for non-GEN9 platforms
+ * below check should be removed.
+ */
+ if (!IS_GEN9(dev_priv))
+ if (WARN_ON_ONCE(!dev_priv->rps.enabled))
+ return -ENODEV;
+
if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
return -ENODEV;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b453852..df56435 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5129,6 +5129,8 @@ static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
static void gen9_disable_rps(struct drm_i915_private *dev_priv)
{
I915_WRITE(GEN6_RP_CONTROL, 0);
+
+ dev_priv->rps.enabled = false;
}
static void gen6_disable_rps(struct drm_i915_private *dev_priv)
@@ -5136,11 +5138,15 @@ static void gen6_disable_rps(struct drm_i915_private *dev_priv)
I915_WRITE(GEN6_RC_CONTROL, 0);
I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
I915_WRITE(GEN6_RP_CONTROL, 0);
+
+ dev_priv->rps.enabled = false;
}
static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
{
I915_WRITE(GEN6_RC_CONTROL, 0);
+
+ dev_priv->rps.enabled = false;
}
static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
@@ -5152,6 +5158,8 @@ static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
I915_WRITE(GEN6_RC_CONTROL, 0);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ dev_priv->rps.enabled = false;
}
static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
@@ -5369,6 +5377,8 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv)
reset_rps(dev_priv, gen6_set_rps);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ dev_priv->rps.enabled = true;
}
static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
@@ -5513,6 +5523,8 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv)
reset_rps(dev_priv, gen6_set_rps);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ dev_priv->rps.enabled = true;
}
static void gen6_enable_rps(struct drm_i915_private *dev_priv)
@@ -5610,6 +5622,8 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
}
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ dev_priv->rps.enabled = true;
}
static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
@@ -6085,6 +6099,8 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
reset_rps(dev_priv, valleyview_set_rps);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ dev_priv->rps.enabled = true;
}
static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
@@ -6166,6 +6182,8 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
reset_rps(dev_priv, valleyview_set_rps);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ dev_priv->rps.enabled = true;
}
static unsigned long intel_pxfreq(u32 vidfreq)
@@ -6737,13 +6755,17 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
{
- if (!READ_ONCE(dev_priv->rps.enabled))
+ if (!IS_GEN9(dev_priv) && !READ_ONCE(dev_priv->rps.enabled))
return;
mutex_lock(&dev_priv->rps.hw_lock);
if (INTEL_GEN(dev_priv) >= 9) {
gen9_disable_rc6(dev_priv);
+ if (!READ_ONCE(dev_priv->rps.enabled)) {
+ mutex_unlock(&dev_priv->rps.hw_lock);
+ return;
+ }
gen9_disable_rps(dev_priv);
} else if (IS_CHERRYVIEW(dev_priv)) {
cherryview_disable_rps(dev_priv);
@@ -6755,7 +6777,6 @@ void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
ironlake_disable_drps(dev_priv);
}
- dev_priv->rps.enabled = false;
mutex_unlock(&dev_priv->rps.hw_lock);
}
@@ -6764,7 +6785,7 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
/* We shouldn't be disabling as we submit, so this should be less
* racy than it appears!
*/
- if (READ_ONCE(dev_priv->rps.enabled))
+ if (!IS_GEN9(dev_priv) && READ_ONCE(dev_priv->rps.enabled))
return;
/* Powersaving is controlled by the host when inside a VM */
@@ -6779,6 +6800,10 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
valleyview_enable_rps(dev_priv);
} else if (INTEL_GEN(dev_priv) >= 9) {
gen9_enable_rc6(dev_priv);
+ if (READ_ONCE(dev_priv->rps.enabled)) {
+ mutex_unlock(&dev_priv->rps.hw_lock);
+ return;
+ }
gen9_enable_rps(dev_priv);
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
gen6_update_ring_freq(dev_priv);
@@ -6799,7 +6824,6 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
- dev_priv->rps.enabled = true;
mutex_unlock(&dev_priv->rps.hw_lock);
}
--
1.9.1
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