[PATCH v5 17/23] drm/i915/slpc: Add i915_slpc_info to debugfs
Sagar Arun Kamble
sagar.a.kamble at intel.com
Sat Oct 22 08:17:14 UTC 2016
From: Tom O'Rourke <Tom.O'Rourke at intel.com>
i915_slpc_info shows the contents of SLPC shared data
parsed into text format.
v1: Reformat slpc info (Radek)
squashed query task state info
in slpc info, kunmap before seq_print (Paulo)
return void instead of ignored return value (Paulo)
Avoid magic numbers and use local variables (Jon Bloomfield)
Removed WARN_ON for checking msb of gtt address of
shared gem obj. (ChrisW)
Moved definition of power plan and power source to earlier
patch in the series.
drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
(Akash)
v2-v3: Rebase.
v4: Updated with GuC firmware v9.
v5: Updated host2guc_slpc_query_task_state with struct slpc_input_event
structure. Removed unnecessary checks of vma from i915_slpc_info and
other misc. changes. (Sagar)
Signed-off-by: Tom O'Rourke <Tom.O'Rourke at intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 189 ++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_slpc.c | 18 ++++
drivers/gpu/drm/i915/intel_slpc.h | 1 +
3 files changed, 208 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 638127c..3608ce4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1259,6 +1259,194 @@ static ssize_t slpc_dcc_write(struct file *file, const char __user *ubuf,
.llseek = seq_lseek
};
+static int i915_slpc_info(struct seq_file *m, void *unused)
+{
+ struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct page *page;
+ void *pv = NULL;
+ struct slpc_shared_data data;
+ struct slpc_task_state_data *task_data;
+ int i, value;
+ enum slpc_global_state global_state;
+ enum slpc_platform_sku platform_sku;
+ enum slpc_power_plan power_plan;
+ enum slpc_power_source power_source;
+
+ if (!dev_priv->guc.slpc.active)
+ return -ENODEV;
+
+ intel_slpc_query_task_state(dev_priv);
+
+ page = i915_vma_first_page(dev_priv->guc.slpc.vma);
+ pv = kmap_atomic(page);
+
+ data = *(struct slpc_shared_data *) pv;
+ kunmap_atomic(pv);
+
+ seq_printf(m, "shared data size: %d\n", data.shared_data_size);
+
+ global_state = (enum slpc_global_state) data.global_state;
+ seq_printf(m, "global state: %d (", global_state);
+ switch (global_state) {
+ case SLPC_GLOBAL_STATE_NOT_RUNNING:
+ seq_puts(m, "not running)\n");
+ break;
+ case SLPC_GLOBAL_STATE_INITIALIZING:
+ seq_puts(m, "initializing)\n");
+ break;
+ case SLPC_GLOBAL_STATE_RESETTING:
+ seq_puts(m, "resetting)\n");
+ break;
+ case SLPC_GLOBAL_STATE_RUNNING:
+ seq_puts(m, "running)\n");
+ break;
+ case SLPC_GLOBAL_STATE_SHUTTING_DOWN:
+ seq_puts(m, "shutting down)\n");
+ break;
+ case SLPC_GLOBAL_STATE_ERROR:
+ seq_puts(m, "error)\n");
+ break;
+ default:
+ seq_puts(m, "unknown)\n");
+ break;
+ }
+
+ platform_sku = (enum slpc_platform_sku)
+ data.platform_info.platform_sku;
+ seq_printf(m, "sku: %d (", platform_sku);
+ switch (platform_sku) {
+ case SLPC_PLATFORM_SKU_UNDEFINED:
+ seq_puts(m, "undefined)\n");
+ break;
+ case SLPC_PLATFORM_SKU_ULX:
+ seq_puts(m, "ULX)\n");
+ break;
+ case SLPC_PLATFORM_SKU_ULT:
+ seq_puts(m, "ULT)\n");
+ break;
+ case SLPC_PLATFORM_SKU_T:
+ seq_puts(m, "T)\n");
+ break;
+ case SLPC_PLATFORM_SKU_MOBL:
+ seq_puts(m, "Mobile)\n");
+ break;
+ case SLPC_PLATFORM_SKU_DT:
+ seq_puts(m, "DT)\n");
+ break;
+ case SLPC_PLATFORM_SKU_UNKNOWN:
+ default:
+ seq_puts(m, "unknown)\n");
+ break;
+ }
+ seq_printf(m, "slice count: %d\n",
+ data.platform_info.slice_count);
+
+ seq_printf(m, "power plan/source: 0x%x\n\tplan:\t",
+ data.platform_info.power_plan_source);
+ power_plan = (enum slpc_power_plan) SLPC_POWER_PLAN(
+ data.platform_info.power_plan_source);
+ power_source = (enum slpc_power_source) SLPC_POWER_SOURCE(
+ data.platform_info.power_plan_source);
+ switch (power_plan) {
+ case SLPC_POWER_PLAN_UNDEFINED:
+ seq_puts(m, "undefined");
+ break;
+ case SLPC_POWER_PLAN_BATTERY_SAVER:
+ seq_puts(m, "battery saver");
+ break;
+ case SLPC_POWER_PLAN_BALANCED:
+ seq_puts(m, "balanced");
+ break;
+ case SLPC_POWER_PLAN_PERFORMANCE:
+ seq_puts(m, "performance");
+ break;
+ case SLPC_POWER_PLAN_UNKNOWN:
+ default:
+ seq_puts(m, "unknown");
+ break;
+ }
+ seq_puts(m, "\n\tsource:\t");
+ switch (power_source) {
+ case SLPC_POWER_SOURCE_UNDEFINED:
+ seq_puts(m, "undefined\n");
+ break;
+ case SLPC_POWER_SOURCE_AC:
+ seq_puts(m, "AC\n");
+ break;
+ case SLPC_POWER_SOURCE_DC:
+ seq_puts(m, "DC\n");
+ break;
+ case SLPC_POWER_SOURCE_UNKNOWN:
+ default:
+ seq_puts(m, "unknown\n");
+ break;
+ }
+
+ seq_printf(m, "IA frequency (MHz):\n\tP0: %d\n\tP1: %d\n\tPe: %d\n\tPn: %d\n",
+ data.platform_info.P0_freq * 50,
+ data.platform_info.P1_freq * 50,
+ data.platform_info.Pe_freq * 50,
+ data.platform_info.Pn_freq * 50);
+
+ task_data = &data.task_state_data;
+ seq_printf(m, "task state data: 0x%08x 0x%08x\n",
+ task_data->bitfield1, task_data->bitfield2);
+
+ seq_printf(m, "\tgtperf task active: %s\n",
+ yesno(task_data->gtperf_task_active));
+ seq_printf(m, "\tgtperf stall possible: %s\n",
+ yesno(task_data->gtperf_stall_possible));
+ seq_printf(m, "\tgtperf gaming mode: %s\n",
+ yesno(task_data->gtperf_gaming_mode));
+ seq_printf(m, "\tgtperf target fps: %d\n",
+ task_data->gtperf_target_fps);
+
+ seq_printf(m, "\tdcc task active: %s\n",
+ yesno(task_data->dcc_task_active));
+ seq_printf(m, "\tin dcc: %s\n",
+ yesno(task_data->in_dcc));
+ seq_printf(m, "\tin dct: %s\n",
+ yesno(task_data->in_dct));
+ seq_printf(m, "\tfreq switch active: %s\n",
+ yesno(task_data->freq_switch_active));
+
+ seq_printf(m, "\tibc enabled: %s\n",
+ yesno(task_data->ibc_enabled));
+ seq_printf(m, "\tibc active: %s\n",
+ yesno(task_data->ibc_active));
+ seq_printf(m, "\tpg1 enabled: %s\n",
+ yesno(task_data->pg1_enabled));
+ seq_printf(m, "\tpg1 active: %s\n",
+ yesno(task_data->pg1_active));
+
+ seq_printf(m, "\tunslice max freq: %dMHz\n",
+ intel_gpu_freq(dev_priv,
+ task_data->freq_unslice_max * GEN9_FREQ_SCALER));
+ seq_printf(m, "\tunslice min freq: %dMHz\n",
+ intel_gpu_freq(dev_priv,
+ task_data->freq_unslice_min * GEN9_FREQ_SCALER));
+ seq_printf(m, "\tslice max freq: %dMHz\n",
+ intel_gpu_freq(dev_priv,
+ task_data->freq_slice_max * GEN9_FREQ_SCALER));
+ seq_printf(m, "\tslice min freq: %dMHz\n",
+ intel_gpu_freq(dev_priv,
+ task_data->freq_slice_min * GEN9_FREQ_SCALER));
+
+ seq_puts(m, "override parameter bitfield\n");
+ for (i = 0; i < SLPC_OVERRIDE_BITFIELD_SIZE; i++)
+ seq_printf(m, "%d: 0x%08x\n", i,
+ data.override_parameters_set_bits[i]);
+
+ seq_puts(m, "override parameters (only non-zero shown)\n");
+ for (i = 0; i < SLPC_MAX_OVERRIDE_PARAMETERS; i++) {
+ value = data.override_parameters_values[i];
+ if (value)
+ seq_printf(m, "%d: 0x%8x\n", i, value);
+ }
+
+ return 0;
+}
+
static int i915_frequency_info(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -5559,6 +5747,7 @@ static int i915_debugfs_create(struct dentry *root,
{"i915_guc_info", i915_guc_info, 0},
{"i915_guc_load_status", i915_guc_load_status_info, 0},
{"i915_guc_log_dump", i915_guc_log_dump, 0},
+ {"i915_slpc_info", i915_slpc_info, 0},
{"i915_frequency_info", i915_frequency_info, 0},
{"i915_hangcheck_info", i915_hangcheck_info, 0},
{"i915_drpc_info", i915_drpc_info, 0},
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 7173ccf..e56f247 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -307,6 +307,24 @@ int slpc_enable_disable_set(struct drm_device *dev, u64 val,
return ret;
}
+static void host2guc_slpc_query_task_state(struct drm_i915_private *dev_priv)
+{
+ struct slpc_event_input data = {0};
+ u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+ data.header.value = SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2);
+ data.args[0] = shared_data_gtt_offset;
+ data.args[1] = 0;
+
+ host2guc_slpc(dev_priv, &data, 4);
+}
+
+void intel_slpc_query_task_state(struct drm_i915_private *dev_priv)
+{
+ if (dev_priv->guc.slpc.active)
+ host2guc_slpc_query_task_state(dev_priv);
+}
+
void intel_slpc_init(struct drm_i915_private *dev_priv)
{
struct intel_guc *guc = &dev_priv->guc;
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 10df947..7633a33 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -237,5 +237,6 @@ int slpc_enable_disable_get(struct drm_device *dev, u64 *val,
u32 enable_id, u32 disable_id);
int slpc_enable_disable_set(struct drm_device *dev, u64 val,
u32 enable_id, u32 disable_id);
+void intel_slpc_query_task_state(struct drm_i915_private *dev_priv);
#endif
--
1.9.1
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