[PATCH v5 20/23] drm/i915/slpc: Don't clear RP_CONTROL while disabling rps

[Sagar Arun Kamble]

While loading, i915 will sanitize PM and hence disable RPS
This leads to clearing of RP_CONTROL register whose value
will be needed for SLPC, Hence don't clear this register if
SLPC is to be enabled.

v5: Not explicitely setting SW Mode control bits for SLPC.
Leaving the RP_CONTROL register value intact through RPS
disabling.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6375317..6292029 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5132,9 +5132,10 @@ static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
 
 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
 {
-	I915_WRITE(GEN6_RP_CONTROL, 0);
-
-	dev_priv->rps.enabled = false;
+	if (!i915.enable_slpc) {
+		I915_WRITE(GEN6_RP_CONTROL, 0);
+		dev_priv->rps.enabled = false;
+	}
 }
 
 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
-- 
1.9.1