[PATCH v5 19/23] drm/i915/slpc: Preserve min/max frequency softlimits on re-activation

Sagar Arun Kamble sagar.a.kamble at intel.com
Sat Oct 22 11:09:29 UTC 2016


v2: Removing checks for vma obj and kmap_atomic validity. (Chris)

v3: Rebase.

v4: Updated to make sure SLPC enable keeps min/max freq softlimits
    unchanged after initializing once. (Chris)

v5: s/first_enable/first_activation

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 45 +++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h |  1 +
 2 files changed, 46 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index fc9f05a..76b8a5a 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -345,6 +345,7 @@ void intel_slpc_init(struct drm_i915_private *dev_priv)
 	}
 
 	slpc_shared_data_init(dev_priv);
+	dev_priv->guc.slpc.first_activation = true;
 }
 
 void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
@@ -372,6 +373,9 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
 void intel_slpc_enable(struct drm_i915_private *dev_priv)
 {
 	u64 val;
+	struct page *page;
+	void *pv = NULL;
+	struct slpc_shared_data data;
 
 	host2guc_slpc_reset(dev_priv);
 
@@ -416,4 +420,45 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv)
 	intel_slpc_set_param(dev_priv,
 			     SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
 			     0);
+
+	if (dev_priv->guc.slpc.first_activation) {
+		intel_slpc_query_task_state(dev_priv);
+
+		page = i915_vma_first_page(dev_priv->guc.slpc.vma);
+		pv = kmap_atomic(page);
+
+		data = *(struct slpc_shared_data *) pv;
+		kunmap_atomic(pv);
+
+		/*
+		 * TODO: Define separate variables for slice and unslice
+		 *	 frequencies for driver state variable.
+		 */
+		dev_priv->rps.max_freq_softlimit =
+				data.task_state_data.freq_unslice_max;
+		dev_priv->rps.min_freq_softlimit =
+				data.task_state_data.freq_unslice_min;
+
+		dev_priv->rps.max_freq_softlimit *= GEN9_FREQ_SCALER;
+		dev_priv->rps.min_freq_softlimit *= GEN9_FREQ_SCALER;
+		dev_priv->guc.slpc.first_activation = false;
+	} else {
+		/* Ask SLPC to operate within min/max freq softlimits */
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+				     intel_gpu_freq(dev_priv,
+					dev_priv->rps.max_freq_softlimit));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+				     intel_gpu_freq(dev_priv,
+					dev_priv->rps.max_freq_softlimit));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+				     intel_gpu_freq(dev_priv,
+					dev_priv->rps.min_freq_softlimit));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+				     intel_gpu_freq(dev_priv,
+					dev_priv->rps.min_freq_softlimit));
+	}
 }
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 7633a33..0c33d14 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -121,6 +121,7 @@ struct slpc_shared_data {
 struct intel_slpc {
 	bool active;
 	struct i915_vma *vma;
+	bool first_activation;
 };
 
 #define SLPC_EVENT_MAX_INPUT_ARGS  7
-- 
1.9.1



More information about the Intel-gfx-trybot mailing list