[PATCH v5 12/23] drm/i915/slpc: Send reset event
Sagar Arun Kamble
sagar.a.kamble at intel.com
Sat Oct 22 11:09:22 UTC 2016
From: Tom O'Rourke <Tom.O'Rourke at intel.com>
Add host2guc SLPC reset event and send reset event
during enable.
v1: Extract host2guc_slpc to handle slpc status code
coding style changes (Paulo)
Removed WARN_ON for checking msb of gtt address of
shared gem obj. (ChrisW)
host2guc_action to i915_guc_action change.(Sagar)
Updating SLPC enabled status. (Sagar)
v2: Commit message update. (David)
v3: Rebase.
v4: Added DRM_INFO message when SLPC is enabled.
v5: Updated patch as host2guc_slpc is moved to earlier patch.
Signed-off-by: Tom O'Rourke <Tom.O'Rourke at intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
---
drivers/gpu/drm/i915/intel_slpc.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 3a0b4a1..6ed8019 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -112,6 +112,18 @@ static void host2guc_slpc(struct drm_i915_private *dev_priv,
DRM_ERROR("event 0x%x status %d\n", (data[1] >> 8), ret);
}
+static void host2guc_slpc_reset(struct drm_i915_private *dev_priv)
+{
+ struct slpc_event_input data = {0};
+ u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+ data.header.value = SLPC_EVENT(SLPC_EVENT_RESET, 2);
+ data.args[0] = shared_data_gtt_offset;
+ data.args[1] = 0;
+
+ host2guc_slpc(dev_priv, &data, 4);
+}
+
void intel_slpc_init(struct drm_i915_private *dev_priv)
{
struct intel_guc *guc = &dev_priv->guc;
@@ -154,4 +166,8 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
void intel_slpc_enable(struct drm_i915_private *dev_priv)
{
+ host2guc_slpc_reset(dev_priv);
+
+ DRM_INFO("SLPC Activated\n");
+ dev_priv->guc.slpc.active = true;
}
--
1.9.1
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