[PATCH 1/1] drm/i915: Disable RPS before GuC is loaded

[Sagar Arun Kamble]

Driver needs to ensure that it doesn't mask the PM interrupts, which are
unmasked by GuC firmware. For that Driver maintains a bitmask of
interrupts to be kept enabled, pm_intr_keep.

RP Up/Down Threshold Interrupt bits (and others) in PMINTRMSK register
were unmasked by default prior to GuC Load. Hence Driver was not masking
these bits assuming GuC needs them.
As an optimization, Driver needs to mask these bits in order to
avoid redundant UP threshold interrupts when frequency is set to maximum,
RP0 or Down threshold interrupts when frequency is set to minimum RPn.
Other bits like ARAT Timer Expired Mask would be kept like earlier.
This patch will disable RPS interrupts and hence mask all bits in
GEN6_PMINTRMSK prior to GuC is loaded in order to maintain pm_intr_keep
only for interrupts that are needed by GuC.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 6fd39ef..04413d8 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -112,6 +112,8 @@ static void guc_interrupts_release(struct drm_i915_private *dev_priv)
 	I915_WRITE(GUC_BCS_RCS_IER, 0);
 	I915_WRITE(GUC_VCS2_VCS1_IER, 0);
 	I915_WRITE(GUC_WD_VECS_IER, 0);
+
+	gen6_disable_rps_interrupts(dev_priv);
 }
 
 static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
-- 
1.9.1