[PATCH 2/3] drm/i915: Handle GEN6_PMINTRMSK for RPS interrupts with GuC

[Chris Wilson]

On Fri, Sep 23, 2016 at 03:22:27PM +0530, Sagar Arun Kamble wrote:
> Driver needs to ensure that it doesn't mask the PM interrupts, which are
> unmasked/needed by GuC firmware. For that, Driver maintains a bitmask of
> interrupts to be kept enabled, pm_intr_keep.
> 
> By default, RP Up/Down Threshold Interrupt bits (and others) in
> GEN6_PMINTRMSK register were unmasked (by BIOS) before GuC Load. Hence
> Driver was keeping them unmasked falsely assuming GuC needed them.
> As an optimization, Driver needs to mask these bits in order to
> avoid redundant UP threshold interrupts when frequency is set to maximum,
> RP0 or Down threshold interrupts when frequency is set to minimum, RPn.
> 
> This patch will mask all bits in GEN6_PMINTRMSK before GuC is loaded to
> ensure pm_intr_keep reflects only interrupts that are needed by GuC. Post
> GuC load, writing cur_freq will restore bits other than pm_intr_keep.
> 
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Testcase: igt/pm_rps/interrupt-config
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem.c  | 13 +++++++++++++
>  drivers/gpu/drm/i915/intel_drv.h |  1 +
>  drivers/gpu/drm/i915/intel_pm.c  |  2 +-
>  3 files changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 1418c1c..7db57ef 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4399,12 +4399,25 @@ i915_gem_init_hw(struct drm_device *dev)
>  
>  	intel_mocs_init_l3cc_table(dev);
>  
> +	/*
> +	 * Mask all interrupts to know which interrupts are needed by GuC.
> +	 * Restore host side interrupt masks post load.
> +	*/
> +	I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));

Random placement. This should be part of the early pm/irq setup.

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2e28d0eb3ee3..c04e8a89d5dc 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -341,6 +341,7 @@ void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
        i915_reg_t reg = gen6_pm_iir(dev_priv);
 
        spin_lock_irq(&dev_priv->irq_lock);
+       I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
        I915_WRITE(reg, dev_priv->pm_rps_events);
        I915_WRITE(reg, dev_priv->pm_rps_events);
        POSTING_READ(reg);

-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre