[PATCH 2/2] drm/i915: Mask GEN6_PMINTRMSK in gen6_reset_rps_interrupts

[Sagar Arun Kamble]

Driver needs to ensure that it doesn't mask the PM interrupts, which are
unmasked/needed by GuC firmware. For that, Driver maintains a bitmask of
interrupts to be kept enabled, pm_intr_keep.

By default, RP Up/Down Threshold Interrupt bits (and others) in
GEN6_PMINTRMSK register were unmasked (by BIOS) before GuC Load. Hence
Driver was keeping them unmasked falsely assuming GuC needed them.
As an optimization, Driver needs to mask these bits in order to
avoid redundant UP threshold interrupts when frequency is set to maximum,
RP0 or Down threshold interrupts when frequency is set to minimum, RPn.

This patch will mask all bits in GEN6_PMINTRMSK before GuC is loaded to
ensure pm_intr_keep reflects only interrupts that are needed by GuC.

Testcase: igt/pm_rps/interrupt-config
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f8c0bea..b619ec5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -341,6 +341,7 @@ void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
 	i915_reg_t reg = gen6_pm_iir(dev_priv);
 
 	spin_lock_irq(&dev_priv->irq_lock);
+	I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
 	I915_WRITE(reg, dev_priv->pm_rps_events);
 	I915_WRITE(reg, dev_priv->pm_rps_events);
 	POSTING_READ(reg);
-- 
1.9.1