[PATCH v3 1/1] drm/i915: Sanitize PMINTRMSK and enable powersave post GuC load on reset

[Sagar Arun Kamble]

Driver needs to ensure that it doesn't mask the PM interrupts, which are
unmasked/needed by GuC firmware. For that, Driver maintains a bitmask of
interrupts to be kept enabled, pm_intr_keep.

By default, RP Up/Down Threshold Interrupt bits (and others) in
GEN6_PMINTRMSK register were unmasked (by BIOS) before GuC Load. Hence
Driver was keeping them unmasked always assuming GuC needed them.
As an optimization, Driver needs to mask these bits in order to
avoid redundant UP threshold interrupts when frequency is set to maximum,
RP0 or Down threshold interrupts when frequency is set to minimum, RPn.

This patch will mask all bits in GEN6_PMINTRMSK before GuC is loaded to
ensure pm_intr_keep reflects only those interrupts that are needed by GuC.
Post GuC load, writing cur_freq will restore bits other than pm_intr_keep.

v2: No functional change. Moving the sanitization of PMINTRMSK inside
    intel_guc_setup. Should take care of scenarios where standalone guc
    setup is done like deferred load in Android. (Sagar)

v3: Sanitizing PMINTRMSK in reset_rps_interrupts. (Chris)
    Moving enable_gt_powersave past gem_init_hw in reset path for GuC
    load to complete. Commit message updated.

Cc: Szwichtenberg, Radoslaw <radoslaw.szwichtenberg at intel.com>
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 6 ++++++
 drivers/gpu/drm/i915/i915_gem.c | 7 +------
 drivers/gpu/drm/i915/i915_irq.c | 1 +
 3 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9c15432..96e31c9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1793,6 +1793,12 @@ void i915_reset(struct drm_i915_private *dev_priv)
 		goto error;
 	}
 
+	if (dev_priv->gt.awake) {
+		intel_enable_gt_powersave(dev_priv);
+		if (INTEL_GEN(dev_priv) >= 6)
+			gen6_rps_busy(dev_priv);
+	}
+
 wakeup:
 	wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS);
 	return;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1418c1c..42b7634 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2629,12 +2629,7 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
 
 	i915_gem_restore_fences(&dev_priv->drm);
 
-	if (dev_priv->gt.awake) {
-		intel_sanitize_gt_powersave(dev_priv);
-		intel_enable_gt_powersave(dev_priv);
-		if (INTEL_GEN(dev_priv) >= 6)
-			gen6_rps_busy(dev_priv);
-	}
+	intel_sanitize_gt_powersave(dev_priv);
 }
 
 static void nop_submit_request(struct drm_i915_gem_request *request)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f8c0bea..b619ec5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -341,6 +341,7 @@ void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
 	i915_reg_t reg = gen6_pm_iir(dev_priv);
 
 	spin_lock_irq(&dev_priv->irq_lock);
+	I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
 	I915_WRITE(reg, dev_priv->pm_rps_events);
 	I915_WRITE(reg, dev_priv->pm_rps_events);
 	POSTING_READ(reg);
-- 
1.9.1