✗ Fi.CI.BAT: failure for series starting with [01/28] drm/i915: Mark CPU cache as dirty on every transition for CPU writes
Patchwork
patchwork at emeril.freedesktop.org
Tue Apr 18 11:52:11 UTC 2017
== Series Details ==
Series: series starting with [01/28] drm/i915: Mark CPU cache as dirty on every transition for CPU writes
URL : https://patchwork.freedesktop.org/series/23165/
State : failure
== Summary ==
Series 23165v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/23165/revisions/1/mbox/
Test gem_exec_fence:
Subgroup await-hang-default:
pass -> INCOMPLETE (fi-hsw-4770) fdo#100672
pass -> INCOMPLETE (fi-ilk-650)
Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass -> DMESG-WARN (fi-snb-2600) fdo#100125
fdo#100672 https://bugs.freedesktop.org/show_bug.cgi?id=100672
fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time:430s
fi-bdw-gvtdvm total:278 pass:256 dwarn:8 dfail:0 fail:0 skip:14 time:423s
fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 time:574s
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:498s
fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time:492s
fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:480s
fi-hsw-4770 total:48 pass:41 dwarn:0 dfail:0 fail:0 skip:6
fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:412s
fi-ilk-650 total:48 pass:27 dwarn:0 dfail:0 fail:0 skip:20
fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:491s
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:473s
fi-kbl-7500u total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:459s
fi-kbl-7560u total:278 pass:267 dwarn:1 dfail:0 fail:0 skip:10 time:565s
fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:445s
fi-skl-6700hq total:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 time:568s
fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time:455s
fi-skl-6770hq total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:487s
fi-skl-gvtdvm total:278 pass:265 dwarn:0 dfail:0 fail:0 skip:13 time:425s
fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:533s
fi-snb-2600 total:278 pass:248 dwarn:1 dfail:0 fail:0 skip:29 time:417s
4d374295ace9e57d83483341e2ad07cad5baf912 drm-tip: 2017y-04m-18d-10h-08m-05s UTC integration manifest
023abac drm/i915: Enable rcu-only context lookups
2a5e3e9 drm/i915: Allow contexts to be unreferenced locklessly
928f213 drm/i915: Group all the global context information together
147c8a1 drm/i915/scheduler: Support user-defined priorities
71a4826 drm/i915: Async GPU relocation processing
6bcf4e2 drm/i915: Allow execbuffer to use the first object as the batch
45eb0b9 drm/i915: Wait upon userptr get-user-pages within execbuffer
5bc6255 drm/i915: First try the previous execbuffer location
7b41269a drm/i915: Eliminate lots of iterations over the execobjects array
698d8a0 drm/i915: Pass vma to relocate entry
6d40f42 drm/i915: Store a direct lookup from object handle to vma
185d34d drm/i915: Split vma exec_link/evict_link
ef9eb4e drm/i915: Use vma->exec_entry as our double-entry placeholder
46f458f drm/i915: Amalgamate execbuffer parameter structures
fa7b614 drm/i915: Reinstate reservation_object zapping for batch_pool objects
f29bbc7 drm/i915: Don't mark an execlists context-switch when idle
e5f6376 drm/i915/execlists: Pack the count into the low bits of the port.request
6b4a5ce drm/i915: Only report a wakeup if the waiter was truly asleep
b9a712a drm/i915: Switch the global i915.semaphores check to a local predicate
8aafe53 drm/i915: Do not record a successful syncpoint for a dma-await
74c133e drm/i915: Confirm the request is still active before adding it to the await
50a6aaa drm/i915: Rename intel_timeline.sync_seqno[] to .global_sync[]
49b4233 drm/i915: Squash repeated awaits on the same fence
97676f2 drm/i915: Redefine ptr_pack_bits() and friends
9be0589 drm/i915: Make ptr_unpack_bits() more function-like
00c1e19 drm/i915: Lift timeline ordering to await_dma_fence
a5cad78 drm/i915: Mark up clflushes as belonging to an unordered timeline
0af6196 drm/i915: Mark CPU cache as dirty on every transition for CPU writes
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Trybot_742/
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