✓ Fi.CI.BAT: success for series starting with [01/31] drm/i915: Mark CPU cache as dirty on every transition for CPU writes
Patchwork
patchwork at emeril.freedesktop.org
Sat Apr 29 14:48:18 UTC 2017
== Series Details ==
Series: series starting with [01/31] drm/i915: Mark CPU cache as dirty on every transition for CPU writes
URL : https://patchwork.freedesktop.org/series/23743/
State : success
== Summary ==
Series 23743v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/23743/revisions/1/mbox/
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time:428s
fi-bdw-gvtdvm total:278 pass:256 dwarn:8 dfail:0 fail:0 skip:14 time:422s
fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 time:569s
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:504s
fi-bxt-t5700 total:278 pass:258 dwarn:0 dfail:0 fail:0 skip:20 time:545s
fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time:488s
fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:477s
fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:408s
fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:411s
fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time:415s
fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:487s
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:489s
fi-kbl-7500u total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:454s
fi-kbl-7560u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:562s
fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:448s
fi-skl-6700hq total:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 time:569s
fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time:452s
fi-skl-6770hq total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:486s
fi-skl-gvtdvm total:278 pass:265 dwarn:0 dfail:0 fail:0 skip:13 time:423s
fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:533s
fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time:404s
1d490e4b6d5324cfbf8dc800cf4a99471252802c drm-tip: 2017y-04m-28d-14h-14m-47s UTC integration manifest
ecbec27 drm/i915/scheduler: Support user-defined priorities
b599c1b drm/i915: Async GPU relocation processing
ee5a42d drm/i915: Allow execbuffer to use the first object as the batch
554684c drm/i915: Wait upon userptr get-user-pages within execbuffer
58d0b6d drm/i915: First try the previous execbuffer location
b83959c drm/i915: Store a persistent reference for an object in the execbuffer cache
9e50baa drm/i915: Eliminate lots of iterations over the execobjects array
e036062 drm/i915: Pass vma to relocate entry
cd4c24f drm/i915: Store a direct lookup from object handle to vma
65fd6b8 drm/i915: Split vma exec_link/evict_link
a16f9d0 drm/i915: Use vma->exec_entry as our double-entry placeholder
7b74b61 drm/i915: Amalgamate execbuffer parameter structures
9f9000b drm/i915: Reinstate reservation_object zapping for batch_pool objects
ec295f7 drm/i915: Split execlist priority queue into rbtree + linked list
d636c4df drm/i915: Use a define for the default priority [0]
f751a98 drm/i915: Don't mark an execlists context-switch when idle
c60679e drm/i915/execlists: Pack the count into the low bits of the port.request
5cc3f10 drm/i915: Redefine ptr_pack_bits() and friends
93a885c drm/i915: Make ptr_unpack_bits() more function-like
ba08f3b drm/i915: Switch the global i915.semaphores check to a local predicate
764a0a1 drm/i915: Do not record a successful syncpoint for a dma-await
a7217eb drm/i915: Rename intel_timeline.sync_seqno[] to .global_sync[]
1def7c4 drm/i915: Squash repeated awaits on the same fence
4f05f92 drm/i915: Lift timeline ordering to await_dma_fence
e4e39e0 drm/i915: Unwrap top level fence-array
d4ea621 drm/i915: Mark up clflushes as belonging to an unordered timeline
20c9b15 drm/i915: Micro-optimise hotpath through intel_ring_begin()
5b29094 drm/i915: Report the ring->space from intel_ring_update_space()
5acddad drm/i915: Avoid the branch in computing intel_ring_space()
97d8384 drm/i915: Store i915_gem_object_is_coherent() as a bit next to cache-dirty
dbb195f drm/i915: Mark CPU cache as dirty on every transition for CPU writes
== Logs ==
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