From: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++++----
drivers/gpu/drm/i915/intel_pipe_crc.c | 34 +++++++++-------------------------
2 files changed, 13 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 09bf043c1c2e..f8f24692acfd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4274,10 +4274,10 @@ enum {
#define DC_BALANCE_RESET (1 << 25)
#define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154)
#define DC_BALANCE_RESET_VLV (1 << 31)
-#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
-#define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
-#define PIPE_B_SCRAMBLE_RESET (1 << 1)
-#define PIPE_A_SCRAMBLE_RESET (1 << 0)
+#define PIPE_SCRAMBLE_RESET_MASK_VLV ((1 << 14) | (0x3 << 0))
+#define PIPE_C_SCRAMBLE_RESET_CHV (1 << 14)
+#define PIPE_B_SCRAMBLE_RESET_VLV (1 << 1)
+#define PIPE_A_SCRAMBLE_RESET_VLV (1 << 0)
/* Gen 3 SDVO bits: */
#define SDVO_ENABLE (1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c
index 1f5cd572a7ff..7457324d576a 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -347,13 +347,13 @@ static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
tmp |= DC_BALANCE_RESET_VLV;
switch (pipe) {
case PIPE_A:
- tmp |= PIPE_A_SCRAMBLE_RESET;
+ tmp |= PIPE_A_SCRAMBLE_RESET_VLV;
break;
case PIPE_B:
- tmp |= PIPE_B_SCRAMBLE_RESET;
+ tmp |= PIPE_B_SCRAMBLE_RESET_VLV;
break;
case PIPE_C:
- tmp |= PIPE_C_SCRAMBLE_RESET;
+ tmp |= PIPE_C_SCRAMBLE_RESET_CHV;
break;
default:
return -EINVAL;
@@ -421,19 +421,10 @@ static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
* - DisplayPort scrambling: used for EMI reduction
*/
if (need_stable_symbols) {
- uint32_t tmp = I915_READ(PORT_DFT2_G4X);
-
WARN_ON(!IS_G4X(dev_priv));
I915_WRITE(PORT_DFT_I9XX,
I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
-
- if (pipe == PIPE_A)
- tmp |= PIPE_A_SCRAMBLE_RESET;
- else
- tmp |= PIPE_B_SCRAMBLE_RESET;
-
- I915_WRITE(PORT_DFT2_G4X, tmp);
}
return 0;
@@ -446,18 +437,18 @@ static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
switch (pipe) {
case PIPE_A:
- tmp &= ~PIPE_A_SCRAMBLE_RESET;
+ tmp &= ~PIPE_A_SCRAMBLE_RESET_VLV;
break;
case PIPE_B:
- tmp &= ~PIPE_B_SCRAMBLE_RESET;
+ tmp &= ~PIPE_B_SCRAMBLE_RESET_VLV;
break;
case PIPE_C:
- tmp &= ~PIPE_C_SCRAMBLE_RESET;
+ tmp &= ~PIPE_C_SCRAMBLE_RESET_CHV;
break;
default:
return;
}
- if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
+ if (!(tmp & PIPE_SCRAMBLE_RESET_MASK_VLV))
tmp &= ~DC_BALANCE_RESET_VLV;
I915_WRITE(PORT_DFT2_G4X, tmp);
@@ -466,15 +457,8 @@ static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
- uint32_t tmp = I915_READ(PORT_DFT2_G4X);
-
- if (pipe == PIPE_A)
- tmp &= ~PIPE_A_SCRAMBLE_RESET;
- else
- tmp &= ~PIPE_B_SCRAMBLE_RESET;
- I915_WRITE(PORT_DFT2_G4X, tmp);
-
- if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
+ /* FIXME */
+ if (1) {
I915_WRITE(PORT_DFT_I9XX,
I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
}
--
2.13.6