[PATCH 20/35] drm/i915: Enable rc6 for Ironlake

Chris Wilson chris at chris-wilson.co.uk
Sat Dec 2 18:34:57 UTC 2017


Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  5 +++-
 drivers/gpu/drm/i915/i915_drv.h     |  2 ++
 drivers/gpu/drm/i915/i915_pci.c     |  3 +--
 drivers/gpu/drm/i915/intel_gt_pm.c  | 53 +++++++++++++++++++++++++++++++++++++
 4 files changed, 60 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 16703be46af3..555d7da51bae 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1402,12 +1402,13 @@ static int i915_reset_info(struct seq_file *m, void *unused)
 static int ironlake_drpc_info(struct seq_file *m)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
-	u32 rgvmodectl, rstdbyctl;
+	u32 rgvmodectl, rstdbyctl, pwrctx;
 	u16 crstandvid;
 
 	rgvmodectl = I915_READ(MEMMODECTL);
 	rstdbyctl = I915_READ(RSTDBYCTL);
 	crstandvid = I915_READ16(CRSTANDVID);
+	pwrctx = I915_READ(PWRCTXA);
 
 	seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
 	seq_printf(m, "Boost freq: %d\n",
@@ -1453,6 +1454,8 @@ static int ironlake_drpc_info(struct seq_file *m)
 		seq_puts(m, "unknown\n");
 		break;
 	}
+	seq_printf(m, "Power context: %x, enabled? %s\n",
+		   pwrctx & ~PWRCTX_EN, yesno(pwrctx & PWRCTX_EN));
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7095b43dce4a..5f591f7e7365 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1407,6 +1407,8 @@ struct intel_gt_pm {
 	 * global mchdev_lock in intel_gt_pm.c
 	 * */
 	struct intel_ips ips;
+
+	struct i915_vma *pctx;
 };
 
 struct drm_i915_private;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index ed5f9d8cdc24..5e2978dba183 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -209,8 +209,7 @@ static const struct intel_device_info intel_gm45_info __initconst = {
 	.has_hotplug = 1, \
 	.ring_mask = RENDER_RING | BSD_RING, \
 	.has_snoop = true, \
-	/* ilk does support rc6, but we do not implement [power] contexts */ \
-	.has_rc6 = 0, \
+	.has_rc6 = true, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c b/drivers/gpu/drm/i915/intel_gt_pm.c
index c5611745b366..82d61ca95299 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/intel_gt_pm.c
@@ -549,6 +549,27 @@ static void gen9_disable_rps(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN6_RP_CONTROL, 0);
 }
 
+static void gen5_enable_rc6(struct drm_i915_private *dev_priv)
+{
+	I915_WRITE(PWRCTXA, i915_ggtt_offset(dev_priv->gt_pm.pctx) | PWRCTX_EN);
+	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
+}
+
+static void gen5_disable_rc6(struct drm_i915_private *dev_priv)
+{
+	/* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
+	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
+	intel_wait_for_register(dev_priv,
+				RSTDBYCTL,
+				RSX_STATUS_MASK, RSX_STATUS_ON,
+				50);
+	I915_WRITE(PWRCTXA, 0);
+	POSTING_READ(PWRCTXA);
+
+	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
+	POSTING_READ(RSTDBYCTL);
+}
+
 static void gen6_disable_rc6(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE(GEN6_RC_CONTROL, 0);
@@ -1390,9 +1411,35 @@ static void ilk_init_frequencies(struct drm_i915_private *i915)
 
 static void gen5_init_gt_powersave(struct drm_i915_private *i915)
 {
+	struct drm_i915_gem_object *obj;
+	struct i915_vma *vma;
+
 	ilk_init_frequencies(i915);
 	ilk_init_emon(i915);
 	ironlake_init_drps(i915);
+
+	obj = i915_gem_object_create_stolen(i915, PAGE_SIZE);
+	if (!obj)
+                obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+	if (IS_ERR(obj))
+		goto err;
+
+	vma = i915_vma_instance(obj, &i915->ggtt.base, NULL);
+	if (IS_ERR(vma))
+		goto err_obj;
+
+	if (i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH))
+		goto err_obj;
+
+	i915->gt_pm.pctx = vma;
+	return;
+
+err_obj:
+	i915_gem_object_put(obj);
+err:
+	DRM_DEBUG_DRIVER("not enough stolen space for PCTX, disabling\n");
+	mkwrite_device_info(i915)->has_rc6 = 0;
+	intel_runtime_pm_get(i915);
 }
 
 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
@@ -2175,6 +2222,8 @@ static void __enable_rc6(struct drm_i915_private *dev_priv)
 		gen8_enable_rc6(dev_priv);
 	else if (INTEL_GEN(dev_priv) >= 6)
 		gen6_enable_rc6(dev_priv);
+	else if (INTEL_GEN(dev_priv) >= 5)
+		gen5_enable_rc6(dev_priv);
 }
 
 static void __enable_rps(struct drm_i915_private *dev_priv)
@@ -2236,6 +2285,8 @@ static void __disable_rc6(struct drm_i915_private *dev_priv)
 		valleyview_disable_rc6(dev_priv);
 	else if (INTEL_GEN(dev_priv) >= 6)
 		gen6_disable_rc6(dev_priv);
+	else if (INTEL_GEN(dev_priv) >= 5)
+		gen5_disable_rc6(dev_priv);
 }
 
 void intel_gt_disable_rc6(struct drm_i915_private *dev_priv)
@@ -2275,6 +2326,8 @@ void intel_gt_pm_fini(struct drm_i915_private *dev_priv)
 	if (IS_VALLEYVIEW(dev_priv))
 		valleyview_cleanup_gt_powersave(dev_priv);
 
+	i915_vma_unpin_and_release(&dev_priv->gt_pm.pctx);
+
 	if (!HAS_RC6(dev_priv))
 		intel_runtime_pm_put(dev_priv);
 }
-- 
2.15.1



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