[PATCH 18/21] drm/i915: Make the RPS interface gen agnostic
Chris Wilson
chris at chris-wilson.co.uk
Sat Dec 9 00:40:41 UTC 2017
This is a preparation patch to change the interface over from gen6+ to
any so that we can extend the RPS infrastructure to support earlier
generations in subsequent patches.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem.c | 18 ++----
drivers/gpu/drm/i915/i915_gem_request.c | 3 +-
drivers/gpu/drm/i915/i915_irq.c | 5 --
drivers/gpu/drm/i915/intel_display.c | 4 +-
drivers/gpu/drm/i915/intel_gt_pm.c | 110 +++++++++++++++-----------------
drivers/gpu/drm/i915/intel_gt_pm.h | 14 ++--
6 files changed, 69 insertions(+), 85 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index aee616d9e42e..64acfaa0e629 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -387,12 +387,8 @@ i915_gem_object_wait_fence(struct dma_fence *fence,
* forcing the clocks too high for the whole system, we only allow
* each client to waitboost once in a busy period.
*/
- if (rps_client) {
- if (INTEL_GEN(rq->i915) >= 6)
- gen6_rps_boost(rq, rps_client);
- else
- rps_client = NULL;
- }
+ if (rps_client)
+ intel_rps_boost(rq, rps_client);
timeout = i915_wait_request(rq, flags, timeout);
@@ -3127,10 +3123,8 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
i915_gem_restore_fences(dev_priv);
intel_gt_enable_rc6(dev_priv);
- if (dev_priv->gt.awake) {
- if (INTEL_GEN(dev_priv) >= 6)
- gen6_rps_busy(dev_priv);
- }
+ if (dev_priv->gt.awake)
+ intel_rps_busy(dev_priv);
}
void i915_gem_reset_finish_engine(struct intel_engine_cs *engine)
@@ -3423,11 +3417,9 @@ i915_gem_idle_work_handler(struct work_struct *work)
dev_priv->gt.awake = false;
rearm_hangcheck = false;
- if (INTEL_GEN(dev_priv) >= 6)
- gen6_rps_idle(dev_priv);
+ intel_rps_idle(dev_priv);
intel_display_power_put(dev_priv, POWER_DOMAIN_GT_IRQ);
-
intel_runtime_pm_put(dev_priv);
out_unlock:
mutex_unlock(&dev_priv->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index 5152f5ab0843..f7849b13d068 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -270,8 +270,7 @@ static void mark_busy(struct drm_i915_private *i915)
i915->gt.awake = true;
i915_update_gfx_val(i915);
- if (INTEL_GEN(i915) >= 6)
- gen6_rps_busy(i915);
+ intel_rps_busy(i915);
i915_pmu_gt_unparked(i915);
intel_engines_unpark(i915);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3517c6548e2c..7dc1c02740ca 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1125,11 +1125,6 @@ static void vlv_c0_read(struct drm_i915_private *dev_priv,
ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
}
-void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
-{
- memset(&dev_priv->gt_pm.rps.ei, 0, sizeof(dev_priv->gt_pm.rps.ei));
-}
-
static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8ed8b912f532..e171726022b6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12603,7 +12603,7 @@ static int do_rps_boost(struct wait_queue_entry *_wait,
struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
struct drm_i915_gem_request *rq = wait->request;
- gen6_rps_boost(rq, NULL);
+ intel_rps_boost(rq, NULL);
i915_gem_request_put(rq);
drm_crtc_vblank_put(wait->crtc);
@@ -12621,7 +12621,7 @@ static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
if (!dma_fence_is_i915(fence))
return;
- if (INTEL_GEN(to_i915(crtc->dev)) < 6)
+ if (!HAS_RPS(to_i915(crtc->dev)))
return;
if (drm_crtc_vblank_get(crtc))
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c b/drivers/gpu/drm/i915/intel_gt_pm.c
index 1ce1d8c08a26..bdcd404846c8 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/intel_gt_pm.c
@@ -50,7 +50,6 @@
* require higher latency to switch to and wake up.
*/
-
/*
* Lock protecting IPS related data structures
*/
@@ -384,43 +383,7 @@ static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
return 0;
}
-/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
- *
- * * If Gfx is Idle, then
- * 1. Forcewake Media well.
- * 2. Request idle freq.
- * 3. Release Forcewake of Media well.
-*/
-static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
-{
- struct intel_rps *rps = &dev_priv->gt_pm.rps;
- u32 val = rps->idle_freq;
- int err;
-
- if (rps->cur_freq <= val)
- return;
-
- /* The punit delays the write of the frequency and voltage until it
- * determines the GPU is awake. During normal usage we don't want to
- * waste power changing the frequency if the GPU is sleeping (rc6).
- * However, the GPU and driver is now idle and we do not want to delay
- * switching to minimum voltage (reducing power whilst idle) as we do
- * not expect to be woken in the near future and so must flush the
- * change by waking the device.
- *
- * We choose to take the media powerwell (either would do to trick the
- * punit into committing the voltage change) as that takes a lot less
- * power than the render powerwell.
- */
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
- err = valleyview_set_rps(dev_priv, val);
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
-
- if (err)
- DRM_ERROR("Failed to set RPS for idle\n");
-}
-
-void gen6_rps_busy(struct drm_i915_private *dev_priv)
+void intel_rps_busy(struct drm_i915_private *dev_priv)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
u8 freq;
@@ -428,16 +391,17 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv)
if (!HAS_RPS(dev_priv))
return;
- mutex_lock(&dev_priv->pcu_lock);
-
- if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED)
- gen6_rps_reset_ei(dev_priv);
- I915_WRITE(GEN6_PMINTRMSK,
- gen6_rps_pm_mask(dev_priv, rps->cur_freq));
+ if (INTEL_GEN(dev_priv) >= 6) {
+ if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED)
+ intel_rps_reset_ei(dev_priv);
+ I915_WRITE(GEN6_PMINTRMSK,
+ gen6_rps_pm_mask(dev_priv, rps->cur_freq));
+ }
- gen6_enable_rps_interrupts(dev_priv);
+ mutex_lock(&dev_priv->pcu_lock);
- /* Use the user's desired frequency as a guide, but for better
+ /*
+ * Use the user's desired frequency as a guide, but for better
* performance, jump directly to RPe as our starting frequency.
*/
freq = max(rps->cur_freq, rps->efficient_freq);
@@ -446,37 +410,62 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv)
rps->min_freq_softlimit,
rps->max_freq_softlimit)))
DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
+
+ rps->last_adj = 0;
mutex_unlock(&dev_priv->pcu_lock);
+
+ if (INTEL_GEN(dev_priv) >= 6)
+ gen6_enable_rps_interrupts(dev_priv);
}
-void gen6_rps_idle(struct drm_i915_private *dev_priv)
+void intel_rps_idle(struct drm_i915_private *dev_priv)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
if (!HAS_RPS(dev_priv))
return;
- /* Flush our bottom-half so that it does not race with us
+ /*
+ * Flush our bottom-half so that it does not race with us
* setting the idle frequency and so that it is bounded by
* our rpm wakeref. And then disable the interrupts to stop any
* futher RPS reclocking whilst we are asleep.
*/
- gen6_disable_rps_interrupts(dev_priv);
+ if (INTEL_GEN(dev_priv) >= 6)
+ gen6_disable_rps_interrupts(dev_priv);
+
+ /*
+ * The punit delays the write of the frequency and voltage until it
+ * determines the GPU is awake. During normal usage we don't want to
+ * waste power changing the frequency if the GPU is sleeping (rc6).
+ * However, the GPU and driver is now idle and we do not want to delay
+ * switching to minimum voltage (reducing power whilst idle) as we do
+ * not expect to be woken in the near future and so must flush the
+ * change by waking the device.
+ *
+ * We choose to take the media powerwell (either would do to trick the
+ * punit into committing the voltage change) as that takes a lot less
+ * power than the render powerwell.
+ */
+ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
mutex_lock(&dev_priv->pcu_lock);
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- vlv_set_rps_idle(dev_priv);
- else
- gen6_set_rps(dev_priv, rps->idle_freq);
- rps->last_adj = 0;
- I915_WRITE(GEN6_PMINTRMSK,
- gen6_sanitize_rps_pm_mask(dev_priv, ~0));
+ if (intel_set_rps(dev_priv, rps->idle_freq))
+ DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
+ rps->last_adj = 0;
mutex_unlock(&dev_priv->pcu_lock);
+
+ if (INTEL_GEN(dev_priv) >= 6) {
+ I915_WRITE(GEN6_PMINTRMSK,
+ gen6_sanitize_rps_pm_mask(dev_priv, ~0));
+ }
+
+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
}
-void gen6_rps_boost(struct drm_i915_gem_request *rq,
+void intel_rps_boost(struct drm_i915_gem_request *rq,
struct intel_rps_client *rps_client)
{
struct intel_rps *rps = &rq->i915->gt_pm.rps;
@@ -508,6 +497,9 @@ int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
struct intel_rps *rps = &dev_priv->gt_pm.rps;
int err;
+ if (!HAS_RPS(dev_priv))
+ return 0;
+
lockdep_assert_held(&dev_priv->pcu_lock);
GEM_BUG_ON(val > rps->max_freq);
GEM_BUG_ON(val < rps->min_freq);
@@ -519,8 +511,10 @@ int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
err = valleyview_set_rps(dev_priv, val);
- else
+ else if (INTEL_GEN(dev_priv) >= 6)
err = gen6_set_rps(dev_priv, val);
+ else
+ err = 0;
return err;
}
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.h b/drivers/gpu/drm/i915/intel_gt_pm.h
index a7a370059b0a..dcc77c034ac7 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/intel_gt_pm.h
@@ -38,11 +38,15 @@ void intel_gt_disable_rps(struct drm_i915_private *dev_priv);
void intel_gt_enable_rc6(struct drm_i915_private *dev_priv);
void intel_gt_disable_rc6(struct drm_i915_private *dev_priv);
-void gen6_rps_busy(struct drm_i915_private *dev_priv);
-void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
-void gen6_rps_idle(struct drm_i915_private *dev_priv);
-void gen6_rps_boost(struct drm_i915_gem_request *rq,
- struct intel_rps_client *rps);
+void intel_rps_busy(struct drm_i915_private *dev_priv);
+void intel_rps_idle(struct drm_i915_private *dev_priv);
+void intel_rps_boost(struct drm_i915_gem_request *rq,
+ struct intel_rps_client *rps);
+
+static inline void intel_rps_reset_ei(struct drm_i915_private *dev_priv)
+{
+ memset(&dev_priv->gt_pm.rps.ei, 0, sizeof(dev_priv->gt_pm.rps.ei));
+}
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
--
2.15.1
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