[PATCH 31/33] drm/i915,intel_ips: Enable GPU wait-boosting with IPS

Chris Wilson chris at chris-wilson.co.uk
Wed Dec 20 22:34:18 UTC 2017


Refactor the reclocking logic used by RPS on Ironlake to reuse the
infrastructure developed for RPS on Sandybridge+, along with the
waitboosting support for stalled clients and missed frames.

v2: Mark rps interrupts as enabled

Reported-by: dimon at gmx.net
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90137
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_debugfs.c     |   1 +
 drivers/gpu/drm/i915/i915_drv.h         |   8 -
 drivers/gpu/drm/i915/i915_gem_request.c |   1 -
 drivers/gpu/drm/i915/i915_irq.c         | 113 +++++-----
 drivers/gpu/drm/i915/i915_sysfs.c       |  10 +
 drivers/gpu/drm/i915/intel_gt_pm.c      | 356 +++++++++++++++++---------------
 drivers/platform/x86/intel_ips.c        |  14 +-
 include/drm/i915_drm.h                  |   1 +
 8 files changed, 268 insertions(+), 236 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index cc07b87269b4..7a5207a0dfbb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1364,6 +1364,7 @@ static int ironlake_drpc_info(struct seq_file *m)
 		   yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
 	seq_printf(m, "SW control enabled: %s\n",
 		   yesno(rgvmodectl & MEMMODE_SWMODE_EN));
+	seq_printf(m, "RPS active? %s\n", yesno(dev_priv->gt.awake));
 	seq_printf(m, "Gated voltage change: %s\n",
 		   yesno(rgvmodectl & MEMMODE_RCLK_GATE));
 	seq_printf(m, "Starting frequency: P%d\n",
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ed82834dca54..5325e1a0db94 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1385,17 +1385,10 @@ struct intel_rps {
 	struct intel_rps_ei ei;
 };
 
-
 /* defined intel_pm.c */
 extern spinlock_t mchdev_lock;
 
 struct intel_ips {
-	u8 cur_delay;
-	u8 min_delay;
-	u8 max_delay;
-	u8 fmax;
-	u8 fstart;
-
 	u64 last_count1;
 	unsigned long last_time1;
 	unsigned long chipset_power;
@@ -3373,7 +3366,6 @@ extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
-extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
 
 int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index 0c02b76b226f..caac6fb0a443 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -269,7 +269,6 @@ static void mark_busy(struct drm_i915_private *i915)
 
 	i915->gt.awake = true;
 
-	i915_update_gfx_val(i915);
 	intel_rps_busy(i915);
 	i915_pmu_gt_unparked(i915);
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f5bcdfa3d7b5..e1f4971ae8e0 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -394,9 +394,13 @@ static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_m
 {
 	lockdep_assert_held(&dev_priv->irq_lock);
 
-	dev_priv->pm_ier &= ~disable_mask;
-	__gen6_mask_pm_irq(dev_priv, disable_mask);
-	I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
+	if (INTEL_INFO(dev_priv)->gen >= 6) {
+		dev_priv->pm_ier &= ~disable_mask;
+		__gen6_mask_pm_irq(dev_priv, disable_mask);
+		I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
+	} else if (IS_IRONLAKE_M(dev_priv)) {
+		ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
+	}
 	/* though a barrier is missing here, but don't really need a one */
 }
 
@@ -434,9 +438,12 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 	spin_lock_irq(&dev_priv->irq_lock);
 	rps->interrupts_enabled = false;
 
-	I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
-
-	gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
+	if (INTEL_GEN(dev_priv) >= 6) {
+		I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
+		gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
+	} else {
+		ilk_disable_display_irq(dev_priv, DE_PCU_EVENT);
+	}
 
 	spin_unlock_irq(&dev_priv->irq_lock);
 	synchronize_irq(dev_priv->drm.irq);
@@ -1025,45 +1032,6 @@ int intel_get_crtc_scanline(struct intel_crtc *crtc)
 	return position;
 }
 
-static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
-{
-	struct intel_ips *ips = &dev_priv->gt_pm.ips;
-	u32 busy_up, busy_down, max_avg, min_avg;
-	u8 new_delay;
-
-	spin_lock(&mchdev_lock);
-
-	I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
-
-	new_delay = ips->cur_delay;
-
-	I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
-	busy_up = I915_READ(RCPREVBSYTUPAVG);
-	busy_down = I915_READ(RCPREVBSYTDNAVG);
-	max_avg = I915_READ(RCBMAXAVG);
-	min_avg = I915_READ(RCBMINAVG);
-
-	/* Handle RCS change request from hw */
-	if (busy_up > max_avg) {
-		if (ips->cur_delay != ips->max_delay)
-			new_delay = ips->cur_delay - 1;
-		if (new_delay < ips->max_delay)
-			new_delay = ips->max_delay;
-	} else if (busy_down < min_avg) {
-		if (ips->cur_delay != ips->min_delay)
-			new_delay = ips->cur_delay + 1;
-		if (new_delay > ips->min_delay)
-			new_delay = ips->min_delay;
-	}
-
-	if (ironlake_set_drps(dev_priv, new_delay))
-		ips->cur_delay = new_delay;
-
-	spin_unlock(&mchdev_lock);
-
-	return;
-}
-
 static void notify_ring(struct intel_engine_cs *engine)
 {
 	struct drm_i915_gem_request *rq = NULL;
@@ -1126,6 +1094,36 @@ static void vlv_c0_read(struct drm_i915_private *dev_priv,
 	ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
 }
 
+static u32 ilk_compute_pm_iir(struct drm_i915_private *dev_priv)
+{
+	u32 pm_iir;
+
+	spin_lock(&mchdev_lock);
+	I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
+	I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
+
+#define busy_up I915_READ(RCPREVBSYTUPAVG)
+#define busy_down I915_READ(RCPREVBSYTDNAVG)
+#define max_avg I915_READ(RCBMAXAVG)
+#define min_avg I915_READ(RCBMINAVG)
+
+	if (busy_up > max_avg)
+		pm_iir = GEN6_PM_RP_UP_THRESHOLD;
+	else if (busy_down < min_avg)
+		pm_iir = GEN6_PM_RP_DOWN_THRESHOLD;
+	else
+		pm_iir = 0;
+
+#undef busy_up
+#undef busy_down
+#undef max_avg
+#undef min_avg
+
+	spin_unlock(&mchdev_lock);
+
+	return pm_iir;
+}
+
 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
 {
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
@@ -1176,15 +1174,15 @@ static void gen6_pm_rps_work(struct work_struct *work)
 	u32 pm_iir = 0;
 
 	spin_lock_irq(&dev_priv->irq_lock);
-	if (rps->interrupts_enabled) {
-		pm_iir = fetch_and_zero(&rps->pm_iir);
-		client_boost = atomic_read(&rps->num_waiters);
-	}
+	if (rps->interrupts_enabled)
+		pm_iir = fetch_and_zero(&rps->pm_iir) & dev_priv->pm_rps_events;
+	if (IS_GEN5(dev_priv))
+		pm_iir = ilk_compute_pm_iir(dev_priv);
+	client_boost = atomic_read(&rps->num_waiters);
 	spin_unlock_irq(&dev_priv->irq_lock);
 
 	/* Make sure we didn't queue anything we're not going to process. */
-	WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
-	if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
+	if (!pm_iir && !client_boost)
 		goto out;
 
 	mutex_lock(&dev_priv->pcu_lock);
@@ -2405,7 +2403,7 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
 	}
 
 	if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
-		ironlake_rps_change_irq_handler(dev_priv);
+		queue_work(dev_priv->wq, &dev_priv->gt_pm.rps.work);
 }
 
 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
@@ -3496,17 +3494,6 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
 
 	ibx_irq_postinstall(dev);
 
-	if (IS_IRONLAKE_M(dev_priv)) {
-		/* Enable PCU event interrupts
-		 *
-		 * spinlocking not required here for correctness since interrupt
-		 * setup is guaranteed to run in single-threaded context. But we
-		 * need it to make the assert_spin_locked happy. */
-		spin_lock_irq(&dev_priv->irq_lock);
-		ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
-		spin_unlock_irq(&dev_priv->irq_lock);
-	}
-
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 75d19749e81b..4a727da4f399 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -479,6 +479,14 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr
 	return snprintf(buf, PAGE_SIZE, "%d\n", val);
 }
 
+static const struct attribute *gen5_attrs[] = {
+	&dev_attr_gt_cur_freq_mhz.attr,
+	&dev_attr_gt_max_freq_mhz.attr,
+	&dev_attr_gt_min_freq_mhz.attr,
+	&dev_attr_gt_RP0_freq_mhz.attr,
+	&dev_attr_gt_RPn_freq_mhz.attr,
+	NULL,
+};
 static const struct attribute *gen6_attrs[] = {
 	&dev_attr_gt_act_freq_mhz.attr,
 	&dev_attr_gt_cur_freq_mhz.attr,
@@ -615,6 +623,8 @@ void i915_setup_sysfs(struct drm_i915_private *dev_priv)
 		ret = sysfs_create_files(&kdev->kobj, vlv_attrs);
 	else if (INTEL_GEN(dev_priv) >= 6)
 		ret = sysfs_create_files(&kdev->kobj, gen6_attrs);
+	else if (INTEL_INFO(dev_priv)->gen >= 5)
+		ret = sysfs_create_files(&kdev->kobj, gen5_attrs);
 	if (ret)
 		DRM_ERROR("RPS sysfs setup failed\n");
 
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c b/drivers/gpu/drm/i915/intel_gt_pm.c
index 05c01c85dc31..8c8932707458 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/intel_gt_pm.c
@@ -49,44 +49,54 @@
  * which brings the most power savings; deeper states save more power, but
  * require higher latency to switch to and wake up.
  */
+static void gen5_update_gfx_val(struct drm_i915_private *dev_priv);
 
 /*
  * Lock protecting IPS related data structures
  */
 DEFINE_SPINLOCK(mchdev_lock);
 
-bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
+static int __ironlake_set_rps(struct drm_i915_private *dev_priv, u8 val)
 {
+	struct intel_rps *rps = &dev_priv->gt_pm.rps;
 	u16 rgvswctl;
 
 	lockdep_assert_held(&mchdev_lock);
 
-	rgvswctl = I915_READ16(MEMSWCTL);
-	if (rgvswctl & MEMCTL_CMD_STS) {
-		DRM_DEBUG("gpu busy, RCS change rejected\n");
-		return false; /* still busy with another command */
+	if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) {
+		DRM_DEBUG_DRIVER("gpu busy, RCS change rejected\n");
+		return -EAGAIN; /* still busy with another command */
 	}
 
-	rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
-		(val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
+	val = rps->max_freq - val + rps->min_freq;
+
+	rgvswctl =
+		(MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
+		(val << MEMCTL_FREQ_SHIFT) |
+		MEMCTL_SFCAVM;
 	I915_WRITE16(MEMSWCTL, rgvswctl);
 	POSTING_READ16(MEMSWCTL);
 
 	rgvswctl |= MEMCTL_CMD_STS;
 	I915_WRITE16(MEMSWCTL, rgvswctl);
 
-	return true;
+	return 0;
+}
+
+static int ironlake_set_rps(struct drm_i915_private *dev_priv, u8 val)
+{
+	spin_lock_irq(&mchdev_lock);
+	__ironlake_set_rps(dev_priv, val);
+	spin_unlock_irq(&mchdev_lock);
+
+	return 0;
 }
 
 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
 {
 	struct intel_ips *ips = &dev_priv->gt_pm.ips;
-	u32 rgvmodectl;
-	u8 fmax, fmin, fstart, vstart;
-
-	spin_lock_irq(&mchdev_lock);
 
-	rgvmodectl = I915_READ(MEMMODECTL);
+	spin_lock(&mchdev_lock);
 
 	/* Enable temp reporting */
 	I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
@@ -102,57 +112,53 @@ static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
 
 	I915_WRITE(MEMIHYST, 1);
 
-	/* Set up min, max, and cur for interrupt handling */
-	fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
-	fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
-	fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
-		MEMMODE_FSTART_SHIFT;
-
-	vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
-		PXVFREQ_PX_SHIFT;
-
-	ips->fmax = fmax; /* IPS callback will increase this */
-	ips->fstart = fstart;
-
-	ips->max_delay = fstart;
-	ips->min_delay = fmin;
-	ips->cur_delay = fstart;
-
-	DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
-			 fmax, fmin, fstart);
-
 	I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
 
-	/*
-	 * Interrupts will be enabled in ironlake_irq_postinstall
-	 */
-
-	I915_WRITE(VIDSTART, vstart);
-	POSTING_READ(VIDSTART);
-
-	rgvmodectl |= MEMMODE_SWMODE_EN;
-	I915_WRITE(MEMMODECTL, rgvmodectl);
-
+	I915_WRITE(MEMMODECTL, I915_READ(MEMMODECTL) | MEMMODE_SWMODE_EN);
 	if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
 		DRM_ERROR("stuck trying to change perf mode\n");
 	mdelay(1);
 
-	ironlake_set_drps(dev_priv, fstart);
-
 	ips->last_count1 =
 		I915_READ(DMIEC) + I915_READ(DDREC) + I915_READ(CSIEC);
 	ips->last_time1 = jiffies_to_msecs(jiffies);
 	ips->last_count2 = I915_READ(GFXEC);
 	ips->last_time2 = ktime_get_raw_ns();
 
-	spin_unlock_irq(&mchdev_lock);
+	spin_unlock(&mchdev_lock);
+}
+
+static void ironlake_init_drps(struct drm_i915_private *dev_priv)
+{
+	struct intel_rps *rps = &dev_priv->gt_pm.rps;
+	u32 rgvmodectl;
+	u8 fmax, fmin, fstart;
+
+	spin_lock(&mchdev_lock);
+	rgvmodectl = I915_READ(MEMMODECTL);
+	spin_unlock(&mchdev_lock);
+
+	/* Set up min, max, and cur for interrupt handling */
+	fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
+	fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
+	fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
+		MEMMODE_FSTART_SHIFT;
+	DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
+			 fmax, fmin, fstart);
+
+	rps->max_freq = fmin;
+	rps->min_freq = fmax;
+	rps->efficient_freq = fmin - fstart;
+
+	I915_WRITE(VIDSTART,
+		   (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
 }
 
 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
 {
 	u16 rgvswctl;
 
-	spin_lock_irq(&mchdev_lock);
+	spin_lock(&mchdev_lock);
 
 	rgvswctl = I915_READ16(MEMSWCTL);
 
@@ -163,14 +169,12 @@ static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
 	I915_WRITE(DEIIR, DE_PCU_EVENT);
 	I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
 
-	/* Go back to the starting frequency */
-	ironlake_set_drps(dev_priv, dev_priv->gt_pm.ips.fstart);
 	mdelay(1);
 	rgvswctl |= MEMCTL_CMD_STS;
 	I915_WRITE(MEMSWCTL, rgvswctl);
 	mdelay(1);
 
-	spin_unlock_irq(&mchdev_lock);
+	spin_unlock(&mchdev_lock);
 }
 
 /* There's a funny hw issue where the hw returns all 0 when reading from
@@ -379,6 +383,8 @@ static int __intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
 		err = valleyview_set_rps(dev_priv, val);
 	else if (INTEL_GEN(dev_priv) >= 6)
 		err = gen6_set_rps(dev_priv, val);
+	else if (INTEL_GEN(dev_priv) >= 5)
+		err = ironlake_set_rps(dev_priv, val);
 	else
 		err = 0;
 
@@ -408,6 +414,8 @@ void intel_rps_busy(struct drm_i915_private *dev_priv)
 
 	if (INTEL_GEN(dev_priv) >= 6)
 		gen6_enable_rps_interrupts(dev_priv);
+	else if (INTEL_GEN(dev_priv) >= 5)
+		gen5_update_gfx_val(dev_priv);
 }
 
 void intel_rps_idle(struct drm_i915_private *dev_priv)
@@ -1267,6 +1275,94 @@ static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
 			 dev_priv->gt_pm.rps.gpll_ref_freq);
 }
 
+static unsigned long ilk_pxfreq(u32 vidfreq)
+{
+	int div = (vidfreq & 0x3f0000) >> 16;
+	int post = (vidfreq & 0x3000) >> 12;
+	int pre = (vidfreq & 0x7);
+
+	if (!pre)
+		return 0;
+
+	return (div * 133333) / (pre << post);
+}
+
+static void ilk_init_emon(struct drm_i915_private *dev_priv)
+{
+	u32 lcfuse;
+	u8 pxw[16];
+	int i;
+
+	/* Disable to program */
+	I915_WRITE(ECR, 0);
+	POSTING_READ(ECR);
+
+	/* Program energy weights for various events */
+	I915_WRITE(SDEW, 0x15040d00);
+	I915_WRITE(CSIEW0, 0x007f0000);
+	I915_WRITE(CSIEW1, 0x1e220004);
+	I915_WRITE(CSIEW2, 0x04000004);
+
+	for (i = 0; i < 5; i++)
+		I915_WRITE(PEW(i), 0);
+	for (i = 0; i < 3; i++)
+		I915_WRITE(DEW(i), 0);
+
+	/* Program P-state weights to account for frequency power adjustment */
+	for (i = 0; i < 16; i++) {
+		u32 pxvidfreq = I915_READ(PXVFREQ(i));
+		unsigned long freq = ilk_pxfreq(pxvidfreq);
+		unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
+			PXVFREQ_PX_SHIFT;
+		unsigned long val;
+
+		val = vid * vid;
+		val *= (freq / 1000);
+		val *= 255;
+		val /= (127*127*900);
+		if (val > 0xff)
+			DRM_ERROR("bad pxval: %ld\n", val);
+		pxw[i] = val;
+	}
+	/* Render standby states get 0 weight */
+	pxw[14] = 0;
+	pxw[15] = 0;
+
+	for (i = 0; i < 4; i++) {
+		u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
+			(pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
+		I915_WRITE(PXW(i), val);
+	}
+
+	/* Adjust magic regs to magic values (more experimental results) */
+	I915_WRITE(OGW0, 0);
+	I915_WRITE(OGW1, 0);
+	I915_WRITE(EG0, 0x00007f00);
+	I915_WRITE(EG1, 0x0000000e);
+	I915_WRITE(EG2, 0x000e0000);
+	I915_WRITE(EG3, 0x68000300);
+	I915_WRITE(EG4, 0x42000000);
+	I915_WRITE(EG5, 0x00140031);
+	I915_WRITE(EG6, 0);
+	I915_WRITE(EG7, 0);
+
+	for (i = 0; i < 8; i++)
+		I915_WRITE(PXWL(i), 0);
+
+	/* Enable PMON + select events */
+	I915_WRITE(ECR, 0x80000019);
+
+	lcfuse = I915_READ(LCFUSE02);
+
+	dev_priv->gt_pm.ips.corr = (lcfuse & LCFUSE_HIV_MASK);
+}
+
+static void gen5_init_gt_powersave(struct drm_i915_private *i915)
+{
+	ilk_init_emon(i915);
+	ironlake_init_drps(i915);
+}
+
 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
 {
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
@@ -1542,21 +1638,6 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 }
 
-static unsigned long intel_pxfreq(u32 vidfreq)
-{
-	unsigned long freq;
-	int div = (vidfreq & 0x3f0000) >> 16;
-	int post = (vidfreq & 0x3000) >> 12;
-	int pre = (vidfreq & 0x7);
-
-	if (!pre)
-		return 0;
-
-	freq = ((div * 133333) / ((1<<post) * pre));
-
-	return freq;
-}
-
 static const struct cparams {
 	u16 i;
 	u16 t;
@@ -1633,11 +1714,11 @@ unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
 		return 0;
 
 	intel_runtime_pm_get(dev_priv);
-	spin_lock_irq(&mchdev_lock);
+	spin_lock(&mchdev_lock);
 
 	val = __i915_chipset_val(dev_priv);
 
-	spin_unlock_irq(&mchdev_lock);
+	spin_unlock(&mchdev_lock);
 	intel_runtime_pm_put(dev_priv);
 
 	return val;
@@ -1714,17 +1795,14 @@ static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
 	ips->gfx_power = diff;
 }
 
-void i915_update_gfx_val(struct drm_i915_private *dev_priv)
+static void gen5_update_gfx_val(struct drm_i915_private *dev_priv)
 {
-	if (INTEL_INFO(dev_priv)->gen != 5)
-		return;
-
 	intel_runtime_pm_get(dev_priv);
-	spin_lock_irq(&mchdev_lock);
+	spin_lock(&mchdev_lock);
 
 	__i915_update_gfx_val(dev_priv);
 
-	spin_unlock_irq(&mchdev_lock);
+	spin_unlock(&mchdev_lock);
 	intel_runtime_pm_put(dev_priv);
 }
 
@@ -1756,7 +1834,7 @@ static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
 
 	corr = corr * ((150142 * state1) / 10000 - 78642);
 	corr /= 100000;
-	corr2 = (corr * ips->corr);
+	corr2 = corr * ips->corr;
 
 	state2 = (corr2 * state1) / 10000;
 	state2 /= 100; /* convert to mW */
@@ -1774,11 +1852,11 @@ unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
 		return 0;
 
 	intel_runtime_pm_get(dev_priv);
-	spin_lock_irq(&mchdev_lock);
+	spin_lock(&mchdev_lock);
 
 	val = __i915_gfx_val(dev_priv);
 
-	spin_unlock_irq(&mchdev_lock);
+	spin_unlock(&mchdev_lock);
 	intel_runtime_pm_put(dev_priv);
 
 	return val;
@@ -1816,8 +1894,10 @@ unsigned long i915_read_mch_val(void)
 
 	intel_runtime_pm_get(i915);
 	spin_lock_irq(&mchdev_lock);
+
 	chipset_val = __i915_chipset_val(i915);
 	graphics_val = __i915_gfx_val(i915);
+
 	spin_unlock_irq(&mchdev_lock);
 	intel_runtime_pm_put(i915);
 
@@ -1834,18 +1914,18 @@ EXPORT_SYMBOL_GPL(i915_read_mch_val);
 bool i915_gpu_raise(void)
 {
 	struct drm_i915_private *i915;
-	struct intel_ips *ips;
+	struct intel_rps *rps;
 
 	i915 = mchdev_get();
 	if (!i915)
 		return false;
 
-	ips = &i915->gt_pm.ips;
+	rps = &i915->gt_pm.rps;
 
-	spin_lock_irq(&mchdev_lock);
-	if (ips->max_delay > ips->fmax)
-		ips->max_delay--;
-	spin_unlock_irq(&mchdev_lock);
+	mutex_lock(&i915->pcu_lock);
+	if (rps->max_freq_softlimit < rps->max_freq)
+		rps->max_freq_softlimit++;
+	mutex_unlock(&i915->pcu_lock);
 
 	drm_dev_put(&i915->drm);
 	return true;
@@ -1861,16 +1941,24 @@ EXPORT_SYMBOL_GPL(i915_gpu_raise);
 bool i915_gpu_lower(void)
 {
 	struct drm_i915_private *i915;
-	struct intel_ips *ips;
+	struct intel_rps *rps;
 
 	i915 = mchdev_get();
 	if (!i915)
 		return false;
 
-	spin_lock_irq(&mchdev_lock);
-	if (ips->max_delay < ips->min_delay)
-		ips->max_delay++;
-	spin_unlock_irq(&mchdev_lock);
+	rps = &i915->gt_pm.rps;
+
+	mutex_lock(&i915->pcu_lock);
+	if (rps->max_freq_softlimit > rps->min_freq)
+		rps->max_freq_softlimit--;
+
+	ironlake_set_rps(i915,
+			 clamp(rps->cur_freq,
+			       rps->min_freq_softlimit,
+			       rps->max_freq_softlimit));
+
+	mutex_unlock(&i915->pcu_lock);
 
 	drm_dev_put(&i915->drm);
 	return true;
@@ -1907,22 +1995,33 @@ EXPORT_SYMBOL_GPL(i915_gpu_busy);
 bool i915_gpu_turbo_disable(void)
 {
 	struct drm_i915_private *i915;
-	bool ret;
 
 	i915 = mchdev_get();
 	if (!i915)
 		return false;
 
-	spin_lock_irq(&mchdev_lock);
-	i915->gt_pm.ips.max_delay = i915->gt_pm.ips.fstart;
-	ret = ironlake_set_drps(i915, i915->gt_pm.ips.fstart);
-	spin_unlock_irq(&mchdev_lock);
+	intel_gt_disable_rps(i915);
 
 	drm_dev_put(&i915->drm);
-	return ret;
+	return true;
 }
 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
 
+bool i915_gpu_turbo_enable(void)
+{
+	struct drm_i915_private *i915;
+
+	i915 = mchdev_get();
+	if (!i915)
+		return false;
+
+	intel_gt_enable_rps(i915);
+
+	drm_dev_put(&i915->drm);
+	return true;
+}
+EXPORT_SYMBOL_GPL(i915_gpu_turbo_enable);
+
 /**
  * Tells the intel_ips driver that the i915 driver is now loaded, if
  * IPS got loaded first.
@@ -1957,76 +2056,6 @@ void intel_gpu_ips_teardown(void)
 	smp_store_mb(i915_mch_dev, NULL);
 }
 
-static void intel_init_emon(struct drm_i915_private *dev_priv)
-{
-	u32 lcfuse;
-	u8 pxw[16];
-	int i;
-
-	/* Disable to program */
-	I915_WRITE(ECR, 0);
-	POSTING_READ(ECR);
-
-	/* Program energy weights for various events */
-	I915_WRITE(SDEW, 0x15040d00);
-	I915_WRITE(CSIEW0, 0x007f0000);
-	I915_WRITE(CSIEW1, 0x1e220004);
-	I915_WRITE(CSIEW2, 0x04000004);
-
-	for (i = 0; i < 5; i++)
-		I915_WRITE(PEW(i), 0);
-	for (i = 0; i < 3; i++)
-		I915_WRITE(DEW(i), 0);
-
-	/* Program P-state weights to account for frequency power adjustment */
-	for (i = 0; i < 16; i++) {
-		u32 pxvidfreq = I915_READ(PXVFREQ(i));
-		unsigned long freq = intel_pxfreq(pxvidfreq);
-		unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
-			PXVFREQ_PX_SHIFT;
-		unsigned long val;
-
-		val = vid * vid;
-		val *= (freq / 1000);
-		val *= 255;
-		val /= (127*127*900);
-		if (val > 0xff)
-			DRM_ERROR("bad pxval: %ld\n", val);
-		pxw[i] = val;
-	}
-	/* Render standby states get 0 weight */
-	pxw[14] = 0;
-	pxw[15] = 0;
-
-	for (i = 0; i < 4; i++) {
-		u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
-			(pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
-		I915_WRITE(PXW(i), val);
-	}
-
-	/* Adjust magic regs to magic values (more experimental results) */
-	I915_WRITE(OGW0, 0);
-	I915_WRITE(OGW1, 0);
-	I915_WRITE(EG0, 0x00007f00);
-	I915_WRITE(EG1, 0x0000000e);
-	I915_WRITE(EG2, 0x000e0000);
-	I915_WRITE(EG3, 0x68000300);
-	I915_WRITE(EG4, 0x42000000);
-	I915_WRITE(EG5, 0x00140031);
-	I915_WRITE(EG6, 0);
-	I915_WRITE(EG7, 0);
-
-	for (i = 0; i < 8; i++)
-		I915_WRITE(PXWL(i), 0);
-
-	/* Enable PMON + select events */
-	I915_WRITE(ECR, 0x80000019);
-
-	lcfuse = I915_READ(LCFUSE02);
-
-	dev_priv->gt_pm.ips.corr = (lcfuse & LCFUSE_HIV_MASK);
-}
-
 void intel_gt_pm_sanitize(struct drm_i915_private *dev_priv)
 {
 	intel_gt_disable_rps(dev_priv);
@@ -2057,6 +2086,8 @@ void intel_gt_pm_init(struct drm_i915_private *dev_priv)
 		valleyview_init_gt_powersave(dev_priv);
 	else if (INTEL_GEN(dev_priv) >= 6)
 		gen6_init_rps_frequencies(dev_priv);
+	else if (INTEL_GEN(dev_priv) >= 5)
+		gen5_init_gt_powersave(dev_priv);
 
 	/* Derive initial user preferences/limits from the hardware limits */
 	rps->idle_freq = rps->min_freq;
@@ -2128,7 +2159,6 @@ static void __enable_rps(struct drm_i915_private *dev_priv)
 		gen6_enable_rps(dev_priv);
 	} else if (INTEL_GEN(dev_priv) >= 5) {
 		ironlake_enable_drps(dev_priv);
-		intel_init_emon(dev_priv);
 	}
 
 	WARN_ON(rps->max_freq < rps->min_freq);
diff --git a/drivers/platform/x86/intel_ips.c b/drivers/platform/x86/intel_ips.c
index a0c95853fd3f..da7443baff55 100644
--- a/drivers/platform/x86/intel_ips.c
+++ b/drivers/platform/x86/intel_ips.c
@@ -336,6 +336,7 @@ struct ips_driver {
 	bool (*gpu_lower)(void);
 	bool (*gpu_busy)(void);
 	bool (*gpu_turbo_disable)(void);
+	bool (*gpu_turbo_enable)(void);
 
 	/* For restoration at unload */
 	u64 orig_turbo_limit;
@@ -575,7 +576,11 @@ static void ips_enable_gpu_turbo(struct ips_driver *ips)
 {
 	if (ips->__gpu_turbo_on)
 		return;
-	ips->__gpu_turbo_on = true;
+
+	if (!ips->gpu_turbo_enable())
+		dev_err(ips->dev, "failed to enable graphics turbo\n");
+	else
+		ips->__gpu_turbo_on = true;
 }
 
 /**
@@ -1432,9 +1437,14 @@ static bool ips_get_i915_syms(struct ips_driver *ips)
 	ips->gpu_turbo_disable = symbol_get(i915_gpu_turbo_disable);
 	if (!ips->gpu_turbo_disable)
 		goto out_put_busy;
+	ips->gpu_turbo_enable = symbol_get(i915_gpu_turbo_enable);
+	if (!ips->gpu_turbo_enable)
+		goto out_put_disable;
 
 	return true;
 
+out_put_disable:
+	symbol_put(i915_gpu_turbo_disable);
 out_put_busy:
 	symbol_put(i915_gpu_busy);
 out_put_lower:
@@ -1676,6 +1686,8 @@ static void ips_remove(struct pci_dev *dev)
 		symbol_put(i915_gpu_busy);
 	if (ips->gpu_turbo_disable)
 		symbol_put(i915_gpu_turbo_disable);
+	if (ips->gpu_turbo_enable)
+		symbol_put(i915_gpu_turbo_enable);
 
 	rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
 	turbo_override &= ~(TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN);
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index c9e5a6621b95..6ee5d77cc923 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -35,6 +35,7 @@ extern bool i915_gpu_raise(void);
 extern bool i915_gpu_lower(void);
 extern bool i915_gpu_busy(void);
 extern bool i915_gpu_turbo_disable(void);
+extern bool i915_gpu_turbo_enable(void);
 
 /* Exported from arch/x86/kernel/early-quirks.c */
 extern struct resource intel_graphics_stolen_res;
-- 
2.15.1



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