[PATCH 29/33] drm/i915: Make the RPS interface gen agnostic

Chris Wilson chris at chris-wilson.co.uk
Wed Dec 20 23:18:37 UTC 2017


This is a preparation patch to change the interface over from gen6+ to
any so that we can extend the RPS infrastructure to support earlier
generations in subsequent patches.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gem.c         | 18 +++++-------------
 drivers/gpu/drm/i915/i915_gem_request.c |  3 +--
 drivers/gpu/drm/i915/i915_irq.c         |  5 -----
 drivers/gpu/drm/i915/intel_display.c    |  4 ++--
 drivers/gpu/drm/i915/intel_gt_pm.c      | 28 +++++++++++++++++-----------
 drivers/gpu/drm/i915/intel_gt_pm.h      |  9 ++++-----
 6 files changed, 29 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index bcbbb4847b61..750bb5f51d0c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -387,12 +387,8 @@ i915_gem_object_wait_fence(struct dma_fence *fence,
 	 * forcing the clocks too high for the whole system, we only allow
 	 * each client to waitboost once in a busy period.
 	 */
-	if (rps_client) {
-		if (INTEL_GEN(rq->i915) >= 6)
-			gen6_rps_boost(rq, rps_client);
-		else
-			rps_client = NULL;
-	}
+	if (rps_client)
+		intel_rps_boost(rq, rps_client);
 
 	timeout = i915_wait_request(rq, flags, timeout);
 
@@ -3151,10 +3147,8 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
 	i915_gem_restore_fences(dev_priv);
 
 	intel_gt_enable_rc6(dev_priv);
-	if (dev_priv->gt.awake) {
-		if (INTEL_GEN(dev_priv) >= 6)
-			gen6_rps_busy(dev_priv);
-	}
+	if (dev_priv->gt.awake)
+		intel_rps_busy(dev_priv);
 }
 
 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine)
@@ -3432,15 +3426,13 @@ i915_gem_idle_work_handler(struct work_struct *work)
 
 	i915_pmu_gt_parked(dev_priv);
 
-	if (INTEL_GEN(dev_priv) >= 6)
-		gen6_rps_idle(dev_priv);
+	intel_rps_idle(dev_priv);
 
 	GEM_BUG_ON(!dev_priv->gt.awake);
 	dev_priv->gt.awake = false;
 	rearm_hangcheck = false;
 
 	intel_display_power_put(dev_priv, POWER_DOMAIN_GT_IRQ);
-
 	intel_runtime_pm_put(dev_priv);
 out_unlock:
 	mutex_unlock(&dev_priv->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index 826a1ce638cb..0c02b76b226f 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -270,8 +270,7 @@ static void mark_busy(struct drm_i915_private *i915)
 	i915->gt.awake = true;
 
 	i915_update_gfx_val(i915);
-	if (INTEL_GEN(i915) >= 6)
-		gen6_rps_busy(i915);
+	intel_rps_busy(i915);
 	i915_pmu_gt_unparked(i915);
 
 	intel_engines_unpark(i915);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3517c6548e2c..7dc1c02740ca 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1125,11 +1125,6 @@ static void vlv_c0_read(struct drm_i915_private *dev_priv,
 	ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
 }
 
-void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
-{
-	memset(&dev_priv->gt_pm.rps.ei, 0, sizeof(dev_priv->gt_pm.rps.ei));
-}
-
 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
 {
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ee9ea02045a1..b00063124917 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12627,7 +12627,7 @@ static int do_rps_boost(struct wait_queue_entry *_wait,
 	struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
 	struct drm_i915_gem_request *rq = wait->request;
 
-	gen6_rps_boost(rq, NULL);
+	intel_rps_boost(rq, NULL);
 	i915_gem_request_put(rq);
 
 	drm_crtc_vblank_put(wait->crtc);
@@ -12645,7 +12645,7 @@ static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
 	if (!dma_fence_is_i915(fence))
 		return;
 
-	if (INTEL_GEN(to_i915(crtc->dev)) < 6)
+	if (!HAS_RPS(to_i915(crtc->dev)))
 		return;
 
 	if (drm_crtc_vblank_get(crtc))
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c b/drivers/gpu/drm/i915/intel_gt_pm.c
index 29d5f7713ae4..c1d88dff23b2 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/intel_gt_pm.c
@@ -50,7 +50,6 @@
  * require higher latency to switch to and wake up.
  */
 
-
 /*
  * Lock protecting IPS related data structures
  */
@@ -381,7 +380,7 @@ static int __intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
 		return 0;
 }
 
-void gen6_rps_busy(struct drm_i915_private *dev_priv)
+void intel_rps_busy(struct drm_i915_private *dev_priv)
 {
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
 	u8 freq;
@@ -391,9 +390,6 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv)
 
 	mutex_lock(&dev_priv->pcu_lock);
 
-	if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED)
-		gen6_rps_reset_ei(dev_priv);
-
 	/*
 	 * Use the user's desired frequency as a guide, but for better
 	 * performance, jump directly to RPe as our starting frequency.
@@ -405,13 +401,16 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv)
 				rps->max_freq_softlimit)))
 		DRM_DEBUG_DRIVER("Failed to set busy frequency\n");
 
+	memset(&rps->ei, 0, sizeof(rps->ei));
 	rps->last_adj = 0;
+
 	mutex_unlock(&dev_priv->pcu_lock);
 
-	gen6_enable_rps_interrupts(dev_priv);
+	if (INTEL_GEN(dev_priv) >= 6)
+		gen6_enable_rps_interrupts(dev_priv);
 }
 
-void gen6_rps_idle(struct drm_i915_private *dev_priv)
+void intel_rps_idle(struct drm_i915_private *dev_priv)
 {
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
 
@@ -424,7 +423,8 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
 	 * our rpm wakeref. And then disable the interrupts to stop any
 	 * futher RPS reclocking whilst we are asleep.
 	 */
-	gen6_disable_rps_interrupts(dev_priv);
+	if (INTEL_GEN(dev_priv) >= 6)
+		gen6_disable_rps_interrupts(dev_priv);
 
 	mutex_lock(&dev_priv->pcu_lock);
 
@@ -449,13 +449,16 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
 		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
 	}
 
-	I915_WRITE(GEN6_PMINTRMSK,
-		   gen6_sanitize_rps_pm_mask(dev_priv, ~0));
+	if (INTEL_GEN(dev_priv) >= 6) {
+		I915_WRITE(GEN6_PMINTRMSK,
+			   gen6_sanitize_rps_pm_mask(dev_priv, ~0));
+	}
 
+	rps->last_adj = 0;
 	mutex_unlock(&dev_priv->pcu_lock);
 }
 
-void gen6_rps_boost(struct drm_i915_gem_request *rq,
+void intel_rps_boost(struct drm_i915_gem_request *rq,
 		    struct intel_rps_client *rps_client)
 {
 	struct intel_rps *rps = &rq->i915->gt_pm.rps;
@@ -486,6 +489,9 @@ int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
 {
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
 
+	if (!HAS_RPS(dev_priv))
+		return 0;
+
 	lockdep_assert_held(&dev_priv->pcu_lock);
 	GEM_BUG_ON(val > rps->max_freq);
 	GEM_BUG_ON(val < rps->min_freq);
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.h b/drivers/gpu/drm/i915/intel_gt_pm.h
index a7a370059b0a..fd2dbe381f32 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/intel_gt_pm.h
@@ -38,11 +38,10 @@ void intel_gt_disable_rps(struct drm_i915_private *dev_priv);
 void intel_gt_enable_rc6(struct drm_i915_private *dev_priv);
 void intel_gt_disable_rc6(struct drm_i915_private *dev_priv);
 
-void gen6_rps_busy(struct drm_i915_private *dev_priv);
-void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
-void gen6_rps_idle(struct drm_i915_private *dev_priv);
-void gen6_rps_boost(struct drm_i915_gem_request *rq,
-		    struct intel_rps_client *rps);
+void intel_rps_busy(struct drm_i915_private *dev_priv);
+void intel_rps_idle(struct drm_i915_private *dev_priv);
+void intel_rps_boost(struct drm_i915_gem_request *rq,
+		     struct intel_rps_client *rps);
 
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
-- 
2.15.1



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