[PATCH 18/23] drm/i915/hsw, bdw: Add pipe_mask, has_vga power well attributes
Imre Deak
imre.deak at intel.com
Wed Jul 5 20:00:35 UTC 2017
The pattern of a power well backing a set of pipes or the VGA
functionality applies to all HSW+ platforms. Using power well attributes
instead of platform checks to decide whether to init/reset pipe IRQs and
VGA is cleaner and it allows us to unify the HSW/BDW and GEN9+ power
well code in follow-up patches.
Signed-off-by: Imre Deak <imre.deak at intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++++
drivers/gpu/drm/i915/intel_runtime_pm.c | 34 ++++++++++++++++++++-------------
2 files changed, 25 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 18a38e56..5538fa4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1391,6 +1391,10 @@ struct i915_power_well {
struct {
enum dpio_phy phy;
} bxt;
+ struct {
+ u32 pipe_mask;
+ bool has_vga:1;
+ } hsw;
};
const struct i915_power_well_ops *ops;
};
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index f6e9d63..118e56b 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -281,7 +281,8 @@ void intel_display_set_init_power(struct drm_i915_private *dev_priv,
* to be enabled, and it will only be disabled if none of the registers is
* requesting it to be enabled.
*/
-static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
+static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
+ u32 pipe_mask, bool has_vga)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
@@ -295,20 +296,21 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
* sure vgacon can keep working normally without triggering interrupts
* and error messages.
*/
- vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
- outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
- vga_put(pdev, VGA_RSRC_LEGACY_IO);
+ if (has_vga) {
+ vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
+ outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
+ vga_put(pdev, VGA_RSRC_LEGACY_IO);
+ }
- if (IS_BROADWELL(dev_priv))
- gen8_irq_power_well_post_enable(dev_priv,
- 1 << PIPE_C | 1 << PIPE_B);
+ if (pipe_mask)
+ gen8_irq_power_well_post_enable(dev_priv, pipe_mask);
}
-static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
+static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
+ u32 pipe_mask)
{
- if (IS_BROADWELL(dev_priv))
- gen8_irq_power_well_pre_disable(dev_priv,
- 1 << PIPE_C | 1 << PIPE_B);
+ if (pipe_mask)
+ gen8_irq_power_well_pre_disable(dev_priv, pipe_mask);
}
static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
@@ -414,7 +416,9 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
HSW_PWR_WELL_CTL_STATE(id),
20))
DRM_ERROR("Timeout enabling power well\n");
- hsw_power_well_post_enable(dev_priv);
+
+ hsw_power_well_post_enable(dev_priv, power_well->hsw.pipe_mask,
+ power_well->hsw.has_vga);
}
static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
@@ -423,7 +427,8 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
enum i915_power_well_id id = power_well->id;
u32 val;
- hsw_power_well_pre_disable(dev_priv);
+ hsw_power_well_pre_disable(dev_priv, power_well->hsw.pipe_mask);
+
val = I915_READ(HSW_PWR_WELL_DRIVER);
I915_WRITE(HSW_PWR_WELL_DRIVER, val & ~HSW_PWR_WELL_CTL_REQ(id));
POSTING_READ(HSW_PWR_WELL_DRIVER);
@@ -2059,6 +2064,7 @@ static struct i915_power_well hsw_power_wells[] = {
.domains = HSW_DISPLAY_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = HSW_DISP_PW_GLOBAL,
+ .hsw.has_vga = true,
},
};
@@ -2075,6 +2081,8 @@ static struct i915_power_well bdw_power_wells[] = {
.domains = BDW_DISPLAY_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = HSW_DISP_PW_GLOBAL,
+ .hsw.pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .hsw.has_vga = true,
},
};
--
2.7.4
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