[PATCH 12/13] drm/i915/skl+: Add debugfs entry for WM info

[Mahesh Kumar]

From: "Kumar, Mahesh" <mahesh1.kumar at intel.com>

This patch adds an entry to print WM values of each enabled plane in
each enabled CRTC.
This will help in debugging any flicker OR WM related issue.

Signed-off-by: Mahesh Kumar <mahesh1.kumar at intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 73 +++++++++++++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 643f56b8b87c..0c0ecdfa06fa 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3588,6 +3588,78 @@ static int i915_wa_registers(struct seq_file *m, void *unused)
 	return 0;
 }
 
+static int i915_wm_info(struct seq_file *m, void *unused)
+{
+	struct drm_i915_private *dev_priv = node_to_i915(m->private);
+	struct drm_device *dev = &dev_priv->drm;
+	struct skl_ddb_allocation *ddb;
+	struct intel_crtc *intel_crtc;
+	struct intel_plane *plane;
+	int l, max_level = ilk_wm_max_level(dev_priv);
+
+	if (INTEL_GEN(dev_priv) < 9)
+		return 0;
+
+
+	seq_printf(m, "%-19s", "");
+	for (l = 0; l <= max_level; l++)
+		seq_printf(m, "%11s%d", "WM L", l);
+	seq_printf(m, "%12s\n", "Trns WM");
+
+	intel_runtime_pm_get(dev_priv);
+	ddb = &dev_priv->wm.skl_hw.ddb;
+	for_each_intel_crtc(dev, intel_crtc) {
+		struct intel_crtc_state *pipe_config;
+		struct skl_pipe_wm *pipe_wm;
+		enum pipe pipe = intel_crtc->pipe;
+
+		drm_modeset_lock(&intel_crtc->base.mutex, NULL);
+		pipe_config = to_intel_crtc_state(intel_crtc->base.state);
+		pipe_wm = &pipe_config->wm.skl.optimal;
+
+		seq_printf(m, "Pipe %c", pipe_name(pipe));
+		if (pipe_config->base.active) {
+			seq_printf(m, " linetime:%d\n", pipe_wm->linetime);
+			for_each_intel_plane_on_crtc(dev, intel_crtc, plane) {
+				struct drm_plane_state *state;
+				struct skl_ddb_entry *entry;
+				struct skl_plane_wm *wm =
+					&pipe_wm->planes[plane->id];
+
+				if (!plane->base.state) {
+					seq_puts(m, "plane->state is NULL!\n");
+					continue;
+				}
+
+				entry = &ddb->plane[pipe][plane->id];
+				state = plane->base.state;
+				seq_printf(m, "  Plane%-2d(%4u) %3s", plane->id,
+						skl_ddb_entry_size(entry),
+						state->visible ? "En" : "Dis");
+
+				for (l = 0; l <= max_level; l++) {
+					struct skl_wm_level *l_wm = &wm->wm[l];
+					seq_printf(m, "%4u|%04u|%02u",
+							l_wm->plane_en,
+							l_wm->plane_res_b,
+							l_wm->plane_res_l);
+				}
+				seq_printf(m, "%4u|%04u|%02u\n",
+						wm->trans_wm.plane_en,
+						wm->trans_wm.plane_res_b,
+						wm->trans_wm.plane_res_l);
+			}
+		}
+
+		seq_printf(m, "\n");
+		drm_modeset_unlock(&intel_crtc->base.mutex);
+	}
+
+	intel_runtime_pm_put(dev_priv);
+
+	return 0;
+}
+
 static int i915_ddb_info(struct seq_file *m, void *unused)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4894,6 +4966,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
 	{"i915_dp_mst_info", i915_dp_mst_info, 0},
 	{"i915_wa_registers", i915_wa_registers, 0},
 	{"i915_ddb_info", i915_ddb_info, 0},
+	{"i915_wm_info", i915_wm_info, 0},
 	{"i915_sseu_status", i915_sseu_status, 0},
 	{"i915_drrs_status", i915_drrs_status, 0},
 	{"i915_rps_boost_info", i915_rps_boost_info, 0},
-- 
2.13.0