[PATCH 05/18] drm/i915/hsw, bdw: Add an ID for the global display power well

[Imre Deak]

Add an ID for the HSW/BDW global display power well for consistency. The
ID is selected so that it can be used to get at the HW request and
status flags with the corresponding GEN9+ macros. Unifying the HSW/BDW
and GEN9+ versions of these macros and the power well ops using them
will be done in follow-up patches.

v2:
- Rebased on v2 of patch 2.

Signed-off-by: Imre Deak <imre.deak at intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 6 ++++++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f9b232e22050..77280da49fba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1098,6 +1098,12 @@ enum i915_power_well_id {
 	CHV_DISP_PW_PIPE_A,			/* 13 */
 
 	/*
+	 * HSW/BDW
+	 *  - HSW_PWR_WELL_DRIVER (status bit: id*2, req bit: id*2+1)
+	 */
+	HSW_DISP_PW_GLOBAL = 15,
+
+	/*
 	 * GEN9+
 	 *  - HSW_PWR_WELL_DRIVER (status bit: id*2, req bit: id*2+1)
 	 */
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 4a9d95505f1b..27c69f9e9df9 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2080,6 +2080,7 @@ static struct i915_power_well hsw_power_wells[] = {
 		.name = "display",
 		.domains = HSW_DISPLAY_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
+		.id = HSW_DISP_PW_GLOBAL,
 	},
 };
 
@@ -2095,6 +2096,7 @@ static struct i915_power_well bdw_power_wells[] = {
 		.name = "display",
 		.domains = BDW_DISPLAY_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
+		.id = HSW_DISP_PW_GLOBAL,
 	},
 };
 
-- 
2.13.2