[PATCH 15/16] drm/i915: accurate page size tracking for the ppgtt

Matthew Auld matthew.auld at intel.com
Tue Jun 6 17:07:47 UTC 2017


Now that we support multiple page sizes for the ppgtt, it would be
useful to track the real usage for debugging purposes.

Signed-off-by: Matthew Auld <matthew.auld at intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c           | 13 +++++++++++++
 drivers/gpu/drm/i915/i915_gem_object.h        |  2 ++
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  1 +
 3 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 62c0e130117a..b7c5e99fc73a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -215,6 +215,8 @@ static int ppgtt_bind_vma(struct i915_vma *vma,
 static void ppgtt_unbind_vma(struct i915_vma *vma)
 {
 	vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
+
+	vma->page_sizes.gtt = 0;
 }
 
 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
@@ -920,6 +922,8 @@ static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm,
 
 	gen8_ppgtt_insert_pte_entries(ppgtt, &ppgtt->pdp, &iter, &idx,
 				      cache_level);
+
+	vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
 }
 
 static void gen8_ppgtt_insert_huge_entries(struct i915_hw_ppgtt *ppgtt,
@@ -1001,11 +1005,14 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_hw_ppgtt *ppgtt,
 				vaddr = kmap_atomic_px(pd);
 				vaddr[idx.pde] |= GEN8_PDE_IPS_64K;
 				kunmap_atomic(vaddr);
+				page_size = I915_GTT_PAGE_SIZE_64K;
 			}
 		}
 
 		idx = gen8_insert_pte(start);
 
+		vma->page_sizes.gtt |= page_size;
+
 	} while (iter->sg);
 }
 
@@ -1030,6 +1037,8 @@ static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
 		while (gen8_ppgtt_insert_pte_entries(ppgtt, pdps[idx.pml4e++],
 						     &iter, &idx, cache_level))
 			GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4);
+
+		vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
 	}
 }
 
@@ -1746,6 +1755,8 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
 		}
 	} while (1);
 	kunmap_atomic(vaddr);
+
+	vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
 }
 
 static int gen6_alloc_va_range(struct i915_address_space *vm,
@@ -2528,6 +2539,8 @@ static void aliasing_gtt_unbind_vma(struct i915_vma *vma)
 		struct i915_address_space *vm = &i915->mm.aliasing_ppgtt->base;
 
 		vm->clear_range(vm, vma->node.start, vma->size);
+
+		vma->page_sizes.gtt = 0;
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/i915_gem_object.h b/drivers/gpu/drm/i915/i915_gem_object.h
index 94a50bf100ac..847a19c5a763 100644
--- a/drivers/gpu/drm/i915/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/i915_gem_object.h
@@ -144,9 +144,11 @@ struct drm_i915_gem_object {
 		struct sg_table *pages;
 		void *mapping;
 
+		/* TODO: whack some of this into the error state */
 		struct i915_page_sizes {
 			unsigned int phys;
 			unsigned int sg;
+			unsigned int gtt;
 		} page_sizes;
 
 		struct i915_gem_object_page_iter {
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 6b132caffa18..31ca81c7f81e 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -272,6 +272,7 @@ static int lowlevel_hole(struct drm_i915_private *i915,
 
 			GEM_BUG_ON(addr + BIT_ULL(size) > vm->total);
 			vm->clear_range(vm, addr, BIT_ULL(size));
+			obj->mm.page_sizes.gtt = 0;
 		}
 
 		i915_gem_object_unpin_pages(obj);
-- 
2.9.4



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