[PATCH] drm/i915: Order irq/breacrumb on gen6 by using the semaphore LRI

Chris Wilson chris at chris-wilson.co.uk
Thu Jun 15 16:36:31 UTC 2017


Jason Ekstrand stumbled over an undocumented (or at least I hadn't
realised) side-effect of the MI register commands that they flush the
earlier pipecontrols and ensure memory ordering. At the very least, it
appears that we can replace the engine->irq_seqno_barrier() entirely by
simply changing the order in which we update the semaphore controls and
our own breadcrumb. Pure magic!

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala at intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 53 +++++++++++++++++++++++++++++++--
 1 file changed, 50 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index acd1da9b62a3..f9c545367b04 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -820,9 +820,6 @@ static void gen8_render_emit_breadcrumb(struct drm_i915_gem_request *req,
 {
 	struct intel_engine_cs *engine = req->engine;
 
-	if (engine->semaphore.signal)
-		cs = engine->semaphore.signal(req, cs);
-
 	*cs++ = GFX_OP_PIPE_CONTROL(6);
 	*cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL |
 		PIPE_CONTROL_QW_WRITE;
@@ -831,6 +828,10 @@ static void gen8_render_emit_breadcrumb(struct drm_i915_gem_request *req,
 	*cs++ = req->global_seqno;
 	/* We're thrashing one dword of HWS. */
 	*cs++ = 0;
+
+	if (engine->semaphore.signal)
+		cs = engine->semaphore.signal(req, cs);
+
 	*cs++ = MI_USER_INTERRUPT;
 	*cs++ = MI_NOOP;
 
@@ -840,6 +841,37 @@ static void gen8_render_emit_breadcrumb(struct drm_i915_gem_request *req,
 
 static const int gen8_render_emit_breadcrumb_sz = 8;
 
+static void gen6_render_emit_breadcrumb(struct drm_i915_gem_request *req,
+					u32 *cs)
+{
+	struct intel_engine_cs *engine = req->engine;
+
+	cs[0] = GFX_OP_PIPE_CONTROL(4);
+	cs[1] = PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
+	cs[2] = intel_hws_seqno_address(engine);
+	cs[3] = req->global_seqno;
+	if (IS_GEN7(req->i915))
+		cs[1] |= PIPE_CONTROL_GLOBAL_GTT_IVB;
+	else
+		cs[2] |= PIPE_CONTROL_GLOBAL_GTT;
+	cs += 4;
+
+	/* Use the signal LRI as a posting flush on the pipecontrol */
+	if (engine->semaphore.signal)
+		cs = engine->semaphore.signal(req, cs);
+
+	*cs++ = MI_LOAD_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
+	*cs++ = i915_mmio_reg_offset(GEN7_3DPRIM_START_INSTANCE);
+	*cs++ = intel_hws_seqno_address(engine);
+
+	*cs++ = MI_USER_INTERRUPT;
+
+	req->tail = intel_ring_offset(req, cs);
+	assert_ring_tail_valid(req->ring, req->tail);
+}
+
+static const int gen6_render_emit_breadcrumb_sz = 8;
+
 /**
  * intel_ring_sync - sync the waiter to the signaller on seqno
  *
@@ -2193,6 +2225,21 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
 		engine->emit_flush = gen7_render_ring_flush;
 		if (IS_GEN6(dev_priv))
 			engine->emit_flush = gen6_render_ring_flush;
+
+		engine->emit_breadcrumb = gen6_render_emit_breadcrumb;
+		engine->emit_breadcrumb_sz = gen6_render_emit_breadcrumb_sz;
+
+		if (i915.semaphores) {
+			int num_rings;
+
+			num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1;
+			engine->emit_breadcrumb_sz += num_rings * 3;
+			if (num_rings & 1)
+				engine->emit_breadcrumb_sz++;
+
+			/* If we have the LRI, seqno/irq are ordered. Magic! */
+			engine->irq_seqno_barrier = NULL;
+		}
 	} else if (IS_GEN5(dev_priv)) {
 		engine->emit_flush = gen4_render_ring_flush;
 	} else {
-- 
2.11.0



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