[PATCH 0/5] gen9+: Sanitize power well disabling during display uninit

Imre Deak imre.deak at intel.com
Thu Jun 29 14:21:15 UTC 2017

This patchset aligns the display uninit sequence with Bspec, wrt. to
disabling power well 1 and the misc IO power well. It also tunes down a
timeout WARN to be a debug message when waiting for power wells to get
disabled while KVMR is active.

Imre Deak (5):
  drm/i915/gen9+: Add 10 us delay after power well 1/AUX IO pw disabling
  drm/i915/skl: Don't disable misc IO power well during display uninit
  drm/i915/bxt,glk: Fix assert on conditions for DC9 enabling
  drm/i915/gen9+: Don't remove secondary power well requests
  drm/i915/cnl: Fix comment about AUX IO power well enable/disable

 drivers/gpu/drm/i915/intel_runtime_pm.c | 137 ++++++++++++++++++++------------
 1 file changed, 85 insertions(+), 52 deletions(-)


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