[PATCH 02/24] drm/i915/gen9: Separate RPS and RC6 handling
Sagar Arun Kamble
sagar.a.kamble at intel.com
Sat Mar 4 08:49:37 UTC 2017
With GuC based SLPC, frequency control will be moved to GuC and Host will
continue to control RC6 and Ring frequency setup. SLPC can be enabled in
the GuC setup path and can happen in parallel in GuC with other i915 setup.
Hence we can do away with deferred RPS enabling. This needs separate
handling of RPS, RC6 and ring frequencies in driver flows. We can still use
the *gt_powersave routines with separate status variables of RPS, RC6 and
SLPC. With this patch, RC6 and ring frequencies setup(if applicable) are
tracked through rps.rc6_enabled and RPS through rps.enabled.
Also, Active RPS check in suspend flow is needed for platforms with RC6
and RPS enabling/disabling coupled together. RPM suspend depends only on
RC6 though. Hence Active RPS check is done only for non-Gen9 platforms.
Moved setting of rps.enabled to platform level functions as there is case
of disabling of RPS in gen9_enable_rps.
v2: Changing parameter to dev_priv for IS_GEN9 and HAS_RUNTIME_PM and line
spacing changes. (David)
and commit message update for checkpatch issues.
v3: Rebase.
v4: Commit message update.
v5: Updated intel_enable_gt_powersave and intel_disable_gt_powersave
routines with separated RPS and RC6 handling and rebase. Commit message
update.(Sagar)
v6: Added comments at the definition of rc6_enabled.
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 6 ++++-
drivers/gpu/drm/i915/i915_drv.h | 5 ++++
drivers/gpu/drm/i915/intel_pm.c | 54 +++++++++++++++++++++++++++++++++--------
3 files changed, 54 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b1e9027..e34cc34 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2363,7 +2363,11 @@ static int intel_runtime_suspend(struct device *kdev)
struct drm_i915_private *dev_priv = to_i915(dev);
int ret;
- if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
+ if (WARN_ON_ONCE(!intel_enable_rc6()))
+ return -ENODEV;
+
+ if (WARN_ON_ONCE((IS_GEN9(dev_priv) && !dev_priv->rps.rc6_enabled) ||
+ (!IS_GEN9(dev_priv) && !dev_priv->rps.enabled)))
return -ENODEV;
if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a6a745b..888a4f7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1374,7 +1374,12 @@ struct intel_gen6_power_mgmt {
struct list_head clients;
bool client_boost;
+ /*
+ * For platforms prior to Gen9, RPS and RC6 status is tracked
+ * through "enabled". For Gen9, RC6 is tracked through "rc6_enabled".
+ */
bool enabled;
+ bool rc6_enabled;
struct delayed_work autoenable_work;
unsigned boosts;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 99e09f6..61c83d2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5387,11 +5387,15 @@ static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
{
I915_WRITE(GEN6_RC_CONTROL, 0);
I915_WRITE(GEN9_PG_ENABLE, 0);
+
+ dev_priv->rps.rc6_enabled = false;
}
static void gen9_disable_rps(struct drm_i915_private *dev_priv)
{
I915_WRITE(GEN6_RP_CONTROL, 0);
+
+ dev_priv->rps.enabled = false;
}
static void gen6_disable_rps(struct drm_i915_private *dev_priv)
@@ -5399,11 +5403,15 @@ static void gen6_disable_rps(struct drm_i915_private *dev_priv)
I915_WRITE(GEN6_RC_CONTROL, 0);
I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
I915_WRITE(GEN6_RP_CONTROL, 0);
+
+ dev_priv->rps.enabled = false;
}
static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
{
I915_WRITE(GEN6_RC_CONTROL, 0);
+
+ dev_priv->rps.enabled = false;
}
static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
@@ -5415,6 +5423,8 @@ static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
I915_WRITE(GEN6_RC_CONTROL, 0);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ dev_priv->rps.enabled = false;
}
static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
@@ -5617,6 +5627,8 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv)
reset_rps(dev_priv, gen6_set_rps);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ dev_priv->rps.enabled = true;
}
static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
@@ -5675,6 +5687,8 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
(GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ dev_priv->rps.rc6_enabled = true;
}
static void gen8_enable_rps(struct drm_i915_private *dev_priv)
@@ -5752,6 +5766,8 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv)
reset_rps(dev_priv, gen6_set_rps);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ dev_priv->rps.enabled = true;
}
static void gen6_enable_rps(struct drm_i915_private *dev_priv)
@@ -5845,6 +5861,8 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
}
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ dev_priv->rps.enabled = true;
}
static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
@@ -6330,6 +6348,8 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
reset_rps(dev_priv, valleyview_set_rps);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ dev_priv->rps.enabled = true;
}
static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
@@ -6411,6 +6431,8 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
reset_rps(dev_priv, valleyview_set_rps);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ dev_priv->rps.enabled = true;
}
static unsigned long intel_pxfreq(u32 vidfreq)
@@ -6975,6 +6997,7 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
{
dev_priv->rps.enabled = true; /* force disabling */
+ dev_priv->rps.rc6_enabled = true;
intel_disable_gt_powersave(dev_priv);
gen6_reset_rps_interrupts(dev_priv);
@@ -6982,14 +7005,20 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
{
- if (!READ_ONCE(dev_priv->rps.enabled))
+ if (!READ_ONCE(dev_priv->rps.enabled)) {
+ if (WARN_ON_ONCE(IS_GEN9(dev_priv) &&
+ READ_ONCE(dev_priv->rps.rc6_enabled)))
+ DRM_ERROR("RC6 not disabled.\n");
return;
+ }
mutex_lock(&dev_priv->rps.hw_lock);
if (INTEL_GEN(dev_priv) >= 9) {
- gen9_disable_rc6(dev_priv);
- gen9_disable_rps(dev_priv);
+ if (READ_ONCE(dev_priv->rps.rc6_enabled))
+ gen9_disable_rc6(dev_priv);
+ if (READ_ONCE(dev_priv->rps.enabled))
+ gen9_disable_rps(dev_priv);
} else if (IS_CHERRYVIEW(dev_priv)) {
cherryview_disable_rps(dev_priv);
} else if (IS_VALLEYVIEW(dev_priv)) {
@@ -7000,7 +7029,6 @@ void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
ironlake_disable_drps(dev_priv);
}
- dev_priv->rps.enabled = false;
mutex_unlock(&dev_priv->rps.hw_lock);
}
@@ -7009,8 +7037,12 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
/* We shouldn't be disabling as we submit, so this should be less
* racy than it appears!
*/
- if (READ_ONCE(dev_priv->rps.enabled))
+ if (READ_ONCE(dev_priv->rps.enabled)) {
+ if (WARN_ON_ONCE(IS_GEN9(dev_priv) &&
+ !READ_ONCE(dev_priv->rps.rc6_enabled)))
+ DRM_ERROR("RC6 and ring frequencies not enabled.\n");
return;
+ }
/* Powersaving is controlled by the host when inside a VM */
if (intel_vgpu_active(dev_priv))
@@ -7023,10 +7055,13 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
} else if (IS_VALLEYVIEW(dev_priv)) {
valleyview_enable_rps(dev_priv);
} else if (INTEL_GEN(dev_priv) >= 9) {
- gen9_enable_rc6(dev_priv);
- gen9_enable_rps(dev_priv);
- if (IS_GEN9_BC(dev_priv))
- gen6_update_ring_freq(dev_priv);
+ if (!READ_ONCE(dev_priv->rps.rc6_enabled)) {
+ gen9_enable_rc6(dev_priv);
+ if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
+ gen6_update_ring_freq(dev_priv);
+ }
+ if (!READ_ONCE(dev_priv->rps.enabled))
+ gen9_enable_rps(dev_priv);
} else if (IS_BROADWELL(dev_priv)) {
gen8_enable_rps(dev_priv);
gen6_update_ring_freq(dev_priv);
@@ -7044,7 +7079,6 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
- dev_priv->rps.enabled = true;
mutex_unlock(&dev_priv->rps.hw_lock);
}
--
1.9.1
More information about the Intel-gfx-trybot
mailing list