[PATCH 16/24] drm/i915/slpc: Add support for min/max frequency control
Sagar Arun Kamble
sagar.a.kamble at intel.com
Wed Mar 8 09:42:56 UTC 2017
Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.
v1: Update for SLPC 2015.2.4 (params for both slice and unslice)
Replace HAS_SLPC with intel_slpc_active() (Paulo)
v2-v4: Rebase.
v5: Removed typecasting the frequency values to u32. (Chris)
Changed intel_slpc_active to guc.slpc.enabled. Carved out
SLPC helpers to set min and max frequencies.
Signed-off-by: Tom O'Rourke <Tom.O'Rourke at intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 +++++++++++++++++++--
drivers/gpu/drm/i915/i915_sysfs.c | 36 ++++++++++++++++++++++++-----
drivers/gpu/drm/i915/intel_slpc.c | 45 +++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_slpc.h | 6 +++++
4 files changed, 105 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e685d07..2ffc08e1 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4302,7 +4302,12 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
if (INTEL_GEN(dev_priv) < 6)
return -ENODEV;
- *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
+ if (dev_priv->guc.slpc.active)
+ *val = intel_gpu_freq(dev_priv,
+ dev_priv->guc.slpc.max_unslice_freq);
+ else
+ *val = intel_gpu_freq(dev_priv,
+ dev_priv->rps.max_freq_softlimit);
return 0;
}
@@ -4327,6 +4332,12 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
*/
val = intel_freq_opcode(dev_priv, val);
+ if (dev_priv->guc.slpc.active) {
+ ret = intel_slpc_max_freq_set(dev_priv, val);
+ mutex_unlock(&dev_priv->rps.hw_lock);
+ return ret;
+ }
+
hw_max = dev_priv->rps.max_freq;
hw_min = dev_priv->rps.min_freq;
@@ -4357,7 +4368,12 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
if (INTEL_GEN(dev_priv) < 6)
return -ENODEV;
- *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
+ if (dev_priv->guc.slpc.active)
+ *val = intel_gpu_freq(dev_priv,
+ dev_priv->guc.slpc.min_unslice_freq);
+ else
+ *val = intel_gpu_freq(dev_priv,
+ dev_priv->rps.min_freq_softlimit);
return 0;
}
@@ -4382,6 +4398,12 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
*/
val = intel_freq_opcode(dev_priv, val);
+ if (dev_priv->guc.slpc.active) {
+ ret = intel_slpc_min_freq_set(dev_priv, val);
+ mutex_unlock(&dev_priv->rps.hw_lock);
+ return ret;
+ }
+
hw_max = dev_priv->rps.max_freq;
hw_min = dev_priv->rps.min_freq;
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index af0ac9f..ca378c2 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -351,9 +351,14 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute
{
struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- return snprintf(buf, PAGE_SIZE, "%d\n",
- intel_gpu_freq(dev_priv,
- dev_priv->rps.max_freq_softlimit));
+ if (dev_priv->guc.slpc.active)
+ return snprintf(buf, PAGE_SIZE, "%d\n",
+ intel_gpu_freq(dev_priv,
+ dev_priv->guc.slpc.max_unslice_freq));
+ else
+ return snprintf(buf, PAGE_SIZE, "%d\n",
+ intel_gpu_freq(dev_priv,
+ dev_priv->rps.max_freq_softlimit));
}
static ssize_t gt_max_freq_mhz_store(struct device *kdev,
@@ -374,6 +379,13 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
val = intel_freq_opcode(dev_priv, val);
+ if (dev_priv->guc.slpc.active) {
+ ret = intel_slpc_max_freq_set(dev_priv, val);
+ mutex_unlock(&dev_priv->rps.hw_lock);
+ intel_runtime_pm_put(dev_priv);
+ return ret ? ret : count;
+ }
+
if (val < dev_priv->rps.min_freq ||
val > dev_priv->rps.max_freq ||
val < dev_priv->rps.min_freq_softlimit) {
@@ -408,9 +420,14 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute
{
struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- return snprintf(buf, PAGE_SIZE, "%d\n",
- intel_gpu_freq(dev_priv,
- dev_priv->rps.min_freq_softlimit));
+ if (dev_priv->guc.slpc.active)
+ return snprintf(buf, PAGE_SIZE, "%d\n",
+ intel_gpu_freq(dev_priv,
+ dev_priv->guc.slpc.min_unslice_freq));
+ else
+ return snprintf(buf, PAGE_SIZE, "%d\n",
+ intel_gpu_freq(dev_priv,
+ dev_priv->rps.min_freq_softlimit));
}
static ssize_t gt_min_freq_mhz_store(struct device *kdev,
@@ -431,6 +448,13 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
val = intel_freq_opcode(dev_priv, val);
+ if (dev_priv->guc.slpc.active) {
+ ret = intel_slpc_min_freq_set(dev_priv, val);
+ mutex_unlock(&dev_priv->rps.hw_lock);
+ intel_runtime_pm_put(dev_priv);
+ return ret ? ret : count;
+ }
+
if (val < dev_priv->rps.min_freq ||
val > dev_priv->rps.max_freq ||
val > dev_priv->rps.max_freq_softlimit) {
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 5224ccb..2ce2940 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -400,6 +400,7 @@ const char *intel_slpc_get_state_str(enum slpc_global_state state)
else
return "unknown";
}
+
bool intel_slpc_get_status(struct drm_i915_private *dev_priv)
{
struct slpc_shared_data data;
@@ -499,6 +500,50 @@ void intel_slpc_get_param(struct drm_i915_private *dev_priv,
kunmap_atomic(data);
}
+/*
+ * TODO: Add separate interfaces to set Max/Min Slice frequency.
+ * Since currently both slice and unslice are configured to same
+ * frequencies these unified interface relying on Unslice frequencies
+ * should be sufficient. These functions take frequency opcode as input.
+ */
+int intel_slpc_max_freq_set(struct drm_i915_private *dev_priv, u32 val)
+{
+ if (val < dev_priv->rps.min_freq ||
+ val > dev_priv->rps.max_freq ||
+ val < dev_priv->guc.slpc.min_unslice_freq)
+ return -EINVAL;
+
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+ intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+ intel_gpu_freq(dev_priv, val));
+
+ dev_priv->guc.slpc.max_unslice_freq = val;
+
+ return 0;
+}
+
+int intel_slpc_min_freq_set(struct drm_i915_private *dev_priv, u32 val)
+{
+ if (val < dev_priv->rps.min_freq ||
+ val > dev_priv->rps.max_freq ||
+ val > dev_priv->guc.slpc.max_unslice_freq)
+ return -EINVAL;
+
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+ intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+ intel_gpu_freq(dev_priv, val));
+
+ dev_priv->guc.slpc.min_unslice_freq = val;
+
+ return 0;
+}
+
void intel_slpc_init(struct drm_i915_private *dev_priv)
{
struct intel_guc *guc = &dev_priv->guc;
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 430e894..bb06e6e 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -124,6 +124,10 @@ struct intel_slpc {
u32 debug_param_id;
u32 debug_param_value;
u32 debug_param_override;
+
+ /* i915 cached SLPC frequency limits */
+ u32 min_unslice_freq;
+ u32 max_unslice_freq;
};
#define SLPC_EVENT_MAX_INPUT_ARGS 7
@@ -241,6 +245,8 @@ void intel_slpc_read_shared_data(struct drm_i915_private *dev_priv,
void intel_slpc_unset_param(struct drm_i915_private *dev_priv, u32 id);
void intel_slpc_get_param(struct drm_i915_private *dev_priv, u32 id,
int *overriding, u32 *value);
+int intel_slpc_max_freq_set(struct drm_i915_private *dev_priv, u32 val);
+int intel_slpc_min_freq_set(struct drm_i915_private *dev_priv, u32 val);
void intel_slpc_init(struct drm_i915_private *dev_priv);
void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
void intel_slpc_enable(struct drm_i915_private *dev_priv);
--
1.9.1
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