[PATCH 06/15] drm/i915: align 64K objects to 2M

[Matthew Auld]

We can't mix 64K and 4K pte's in the same page-table, so for now we
align 64K objects to 2M to avoid any potential mixing. This is
potentially wasteful but in reality shouldn't be too bad since this only
applies to the virtual address space of a 48b PPGTT.

Suggested-by: Chris Wilson <chris at chris-wilson.co.uk>
Signed-off-by: Matthew Auld <matthew.auld at intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
---
 drivers/gpu/drm/i915/i915_vma.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index eb2d1e59b88a..879560c42021 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -479,6 +479,15 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
 			goto err_unpin;
 		}
 
+		/* A current limitation in our implementation is that 64K
+		 * objects must be aligned to 2M, and given that we can't
+		 * enforce this for soft pinning, we need to fallback to normal
+		 * pages if don't meet this restriction.
+		 */
+		if (obj->mm.gtt_page_sizes == I915_GTT_PAGE_SIZE_64K &&
+		    !IS_ALIGNED(offset | size, I915_GTT_PAGE_SIZE_2M))
+			obj->mm.gtt_page_sizes = I915_GTT_PAGE_SIZE;
+
 		ret = i915_gem_gtt_reserve(vma->vm, &vma->node,
 					   size, offset, obj->cache_level,
 					   flags);
@@ -490,6 +499,15 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
 			unsigned int page_alignment =
 				BIT(fls64(obj->mm.gtt_page_sizes)-1);
 
+			/* We can't mix 64K and 4K pte's in the same page-table (2M
+			 * block), and so to avoid the ugliness and complexity of
+			 * coloring we opt for just aligning 64K objects to 2M.
+			 */
+			if (obj->mm.gtt_page_sizes == I915_GTT_PAGE_SIZE_64K) {
+				page_alignment = I915_GTT_PAGE_SIZE_2M;
+				size = roundup(size, page_alignment);
+			}
+
 			alignment = max_t(typeof(alignment), alignment,
 					  page_alignment);
 		}
-- 
2.9.4