[PATCH 11/11] f2
Chris Wilson
chris at chris-wilson.co.uk
Sun Nov 5 12:38:43 UTC 2017
---
drivers/gpu/drm/i915/i915_drv.c | 31 +++++++++------
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 2 -
drivers/gpu/drm/i915/i915_gem_gtt.c | 14 +++----
drivers/gpu/drm/i915/i915_gem_stolen.c | 4 +-
drivers/gpu/drm/i915/intel_cdclk.c | 65 ++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_display.c | 54 -------------------------
drivers/gpu/drm/i915/intel_drv.h | 9 +----
drivers/gpu/drm/i915/intel_pm.c | 73 ++++++++++------------------------
9 files changed, 111 insertions(+), 143 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index fe9e539b6c29..d72113f661a6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -632,8 +632,6 @@ static void i915_gem_fini(struct drm_i915_private *dev_priv)
i915_gem_drain_freed_objects(dev_priv);
WARN_ON(!list_empty(&dev_priv->contexts.list));
-
- intel_cleanup_gt_powersave(dev_priv);
}
static int i915_load_modeset_init(struct drm_device *dev)
@@ -664,9 +662,6 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (ret)
goto cleanup_vga_client;
- /* must happen before intel_power_domains_init_hw() on VLV/CHV */
- intel_update_rawclk(dev_priv);
-
intel_power_domains_init_hw(dev_priv, false);
intel_csr_ucode_init(dev_priv);
@@ -1028,19 +1023,33 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
goto err_bridge;
intel_uncore_init(dev_priv);
+ intel_device_info_runtime_init(dev_priv);
+
+ intel_init_czclk(dev_priv);
+ intel_init_rawclk(dev_priv);
+
+ ret = i915_ggtt_probe_hw(dev_priv);
+ if (ret)
+ goto err_uncore;
+
+ intel_init_gt_powersave(dev_priv);
intel_uc_init_mmio(dev_priv);
ret = intel_engines_init_mmio(dev_priv);
if (ret)
- goto err_uncore;
+ goto err_gt;
i915_gem_init_mmio(dev_priv);
return 0;
+err_gt:
+ intel_cleanup_gt_powersave(dev_priv);
+ i915_ggtt_cleanup_hw(dev_priv);
err_uncore:
intel_uncore_fini(dev_priv);
+ i915_mmio_cleanup(dev_priv);
err_bridge:
pci_dev_put(dev_priv->bridge_dev);
@@ -1053,6 +1062,8 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
*/
static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
{
+ intel_cleanup_gt_powersave(dev_priv);
+ i915_ggtt_cleanup_hw(dev_priv);
intel_uncore_fini(dev_priv);
i915_mmio_cleanup(dev_priv);
pci_dev_put(dev_priv->bridge_dev);
@@ -1100,14 +1111,8 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
if (i915_inject_load_failure())
return -ENODEV;
- intel_device_info_runtime_init(dev_priv);
-
intel_sanitize_options(dev_priv);
- ret = i915_ggtt_probe_hw(dev_priv);
- if (ret)
- return ret;
-
/* WARNING: Apparently we must kick fbdev drivers before vgacon,
* otherwise the vga fbdev driver falls over. */
ret = i915_kick_out_firmware_fb(dev_priv);
@@ -1126,6 +1131,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
if (ret)
return ret;
+
ret = i915_ggtt_enable_hw(dev_priv);
if (ret) {
DRM_ERROR("failed to enable GGTT\n");
@@ -1213,7 +1219,6 @@ static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
pci_disable_msi(pdev);
pm_qos_remove_request(&dev_priv->pm_qos);
- i915_ggtt_cleanup_hw(dev_priv);
}
/**
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2951555dd3c9..a3d2dd777ca5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1360,7 +1360,6 @@ struct intel_rps {
u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
u8 rp1_freq; /* "less than" RP0 power/freqency */
u8 rp0_freq; /* Non-overclocked max frequency. */
- u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
u8 up_threshold; /* Current %busy required to uplock */
u8 down_threshold; /* Current %busy required to downclock */
@@ -2345,6 +2344,7 @@ struct drm_i915_private {
unsigned int rawclk_freq;
unsigned int hpll_freq;
unsigned int czclk_freq;
+ unsigned int gpll_freq; /* vlv/chv GPLL reference frequency */
struct {
/*
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 74f230652029..4075f7d1867f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5134,8 +5134,6 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
if (ret)
goto out_unlock;
- intel_init_gt_powersave(dev_priv);
-
ret = i915_gem_init_hw(dev_priv);
if (ret)
goto out_unlock;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0684d5df97d9..30c9d858adab 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3503,7 +3503,11 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
if (intel_vtd_active())
DRM_INFO("VT-d active for gfx access\n");
- return 0;
+ /*
+ * Initialise stolen early so that we may reserve preallocated
+ * objects for the BIOS to KMS transition.
+ */
+ return i915_gem_init_stolen(dev_priv);
}
/**
@@ -3537,14 +3541,6 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base, ggtt->mappable_end);
- /*
- * Initialise stolen early so that we may reserve preallocated
- * objects for the BIOS to KMS transition.
- */
- ret = i915_gem_init_stolen(dev_priv);
- if (ret)
- goto out_gtt_cleanup;
-
return 0;
out_gtt_cleanup:
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 03e7abc7e043..a6f89be75195 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -657,8 +657,6 @@ i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv
if (!drm_mm_initialized(&dev_priv->mm.stolen))
return NULL;
- lockdep_assert_held(&dev_priv->drm.struct_mutex);
-
DRM_DEBUG_KMS("creating preallocated stolen object: stolen_offset=%x, gtt_offset=%x, size=%x\n",
stolen_offset, gtt_offset, size);
@@ -695,6 +693,8 @@ i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv
if (gtt_offset == I915_GTT_OFFSET_NONE)
return obj;
+ lockdep_assert_held(&dev_priv->drm.struct_mutex);
+
ret = i915_gem_object_pin_pages(obj);
if (ret)
goto err;
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index e8884c2ade98..1e466de72c91 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -456,6 +456,38 @@ static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
}
}
+static int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
+{
+ int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
+
+ /* Obtain SKU information */
+ mutex_lock(&dev_priv->sb_lock);
+ hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
+ CCK_FUSE_HPLL_FREQ_MASK;
+ mutex_unlock(&dev_priv->sb_lock);
+
+ return vco_freq[hpll_freq] * 1000;
+}
+
+static int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
+ const char *name, u32 reg, int ref_freq)
+{
+ u32 val;
+ int divider;
+
+ mutex_lock(&dev_priv->sb_lock);
+ val = vlv_cck_read(dev_priv, reg);
+ mutex_unlock(&dev_priv->sb_lock);
+
+ divider = val & CCK_FREQUENCY_VALUES;
+
+ WARN((val & CCK_FREQUENCY_STATUS) !=
+ (divider << CCK_FREQUENCY_STATUS_SHIFT),
+ "%s change in progress\n", name);
+
+ return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
+}
+
static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_state *cdclk_state)
{
@@ -2272,6 +2304,14 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
dev_priv->max_dotclk_freq);
}
+static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
+ const char *name, u32 reg)
+{
+ return vlv_get_cck_clock(dev_priv, name, reg,
+ dev_priv->hpll_freq);
+}
+
+
/**
* intel_update_cdclk - Determine the current CDCLK frequency
* @dev_priv: i915 device
@@ -2356,15 +2396,14 @@ static int g4x_hrawclk(struct drm_i915_private *dev_priv)
}
/**
- * intel_update_rawclk - Determine the current RAWCLK frequency
+ * intel_init_rawclk - Determine the current RAWCLK frequency
* @dev_priv: i915 device
*
* Determine the current RAWCLK frequency. RAWCLK is a fixed
* frequency clock so this needs to done only once.
*/
-void intel_update_rawclk(struct drm_i915_private *dev_priv)
+void intel_init_rawclk(struct drm_i915_private *dev_priv)
{
-
if (HAS_PCH_CNP(dev_priv))
dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
else if (HAS_PCH_SPLIT(dev_priv))
@@ -2460,3 +2499,23 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
}
}
+
+void intel_init_czclk(struct drm_i915_private *dev_priv)
+{
+ if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
+ return;
+
+ dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
+
+ dev_priv->czclk_freq =
+ vlv_get_cck_clock_hpll(dev_priv, "czclk", CCK_CZ_CLOCK_CONTROL);
+
+ DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
+
+ dev_priv->gpll_freq =
+ vlv_get_cck_clock(dev_priv, "GPLL ref", CCK_GPLL_CLOCK_CONTROL,
+ dev_priv->czclk_freq);
+
+ DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
+ dev_priv->gpll_freq);
+}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index de91a17c9a47..2a556815385e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -160,59 +160,6 @@ struct intel_limit {
};
/* returns HPLL frequency in kHz */
-int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
-{
- int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
-
- /* Obtain SKU information */
- mutex_lock(&dev_priv->sb_lock);
- hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
- CCK_FUSE_HPLL_FREQ_MASK;
- mutex_unlock(&dev_priv->sb_lock);
-
- return vco_freq[hpll_freq] * 1000;
-}
-
-int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
- const char *name, u32 reg, int ref_freq)
-{
- u32 val;
- int divider;
-
- mutex_lock(&dev_priv->sb_lock);
- val = vlv_cck_read(dev_priv, reg);
- mutex_unlock(&dev_priv->sb_lock);
-
- divider = val & CCK_FREQUENCY_VALUES;
-
- WARN((val & CCK_FREQUENCY_STATUS) !=
- (divider << CCK_FREQUENCY_STATUS_SHIFT),
- "%s change in progress\n", name);
-
- return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
-}
-
-int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
- const char *name, u32 reg)
-{
- if (dev_priv->hpll_freq == 0)
- dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
-
- return vlv_get_cck_clock(dev_priv, name, reg,
- dev_priv->hpll_freq);
-}
-
-static void intel_update_czclk(struct drm_i915_private *dev_priv)
-{
- if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
- return;
-
- dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
- CCK_CZ_CLOCK_CONTROL);
-
- DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
-}
-
static inline u32 /* units of 100MHz */
intel_fdi_link_freq(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *pipe_config)
@@ -14542,7 +14489,6 @@ int intel_modeset_init(struct drm_device *dev)
intel_shared_dpll_init(dev);
- intel_update_czclk(dev_priv);
intel_modeset_init_hw(dev);
if (dev_priv->max_cdclk_freq == 0)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bf6ad90624e2..f993c1b237be 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1330,7 +1330,8 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
void intel_update_cdclk(struct drm_i915_private *dev_priv);
-void intel_update_rawclk(struct drm_i915_private *dev_priv);
+void intel_init_rawclk(struct drm_i915_private *dev_priv);
+void intel_init_czclk(struct drm_i915_private *dev_priv);
bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
const struct intel_cdclk_state *b);
bool intel_cdclk_changed(const struct intel_cdclk_state *a,
@@ -1344,12 +1345,6 @@ void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
-void intel_update_rawclk(struct drm_i915_private *dev_priv);
-int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
-int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
- const char *name, u32 reg, int ref_freq);
-int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
- const char *name, u32 reg);
void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
void intel_init_display_hooks(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3d9b0b7c4a5e..1c936c84df7b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7028,24 +7028,6 @@ static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
return max_t(u32, val, 0xc0);
}
-/* Check that the pctx buffer wasn't move under us. */
-static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
-{
- unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
-
- WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
- dev_priv->gt_pm.rc6.pctx->stolen->start);
-}
-
-
-/* Check that the pcbr address is not empty. */
-static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
-{
- unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
-
- WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
-}
-
static void vlv_reserve_pctx(struct drm_i915_private *dev_priv, int pctx_size)
{
struct drm_i915_gem_object *pctx;
@@ -7054,13 +7036,12 @@ static void vlv_reserve_pctx(struct drm_i915_private *dev_priv, int pctx_size)
pcbr = I915_READ(VLV_PCBR);
if (pcbr) {
/* BIOS set it up already, grab the pre-alloc'd space */
- u32 start = round_down(pcbr, 4096);
- u32 end = round_up(pcbr + pctx_size, 4096);
+ u32 offset = round_down(pcbr, 4096) - dev_priv->mm.stolen_base;
pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv,
- start - dev_priv->mm.stolen_base,
+ offset,
I915_GTT_OFFSET_NONE,
- end - start);
+ pctx_size);
} else {
DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
@@ -7075,7 +7056,7 @@ static void vlv_reserve_pctx(struct drm_i915_private *dev_priv, int pctx_size)
pctx = i915_gem_object_create_stolen(dev_priv, pctx_size);
if (!pctx) {
DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
- return;
+ goto out;
}
I915_WRITE(VLV_PCBR,
@@ -7083,9 +7064,20 @@ static void vlv_reserve_pctx(struct drm_i915_private *dev_priv, int pctx_size)
}
DRM_DEBUG_DRIVER("PCBR: 0x%08x [0x%08x]\n", I915_READ(VLV_PCBR), pcbr);
+out:
+ if (!pctx)
+ DRM_ERROR("Failed to reserve memory for the power context; (PCBR: 0x%08x, size %d KiB; stolen base 0x%08x)\n", pcbr, pctx_size >> 10, (u32)dev_priv->mm.stolen_base);
dev_priv->gt_pm.rc6.pctx = pctx;
}
+static void vlv_check_pctx(struct drm_i915_private *dev_priv)
+{
+ u32 pctx_addr = I915_READ(VLV_PCBR) & ~4095;
+
+ WARN_ON(pctx_addr - dev_priv->mm.stolen_base !=
+ dev_priv->gt_pm.rc6.pctx->stolen->start);
+}
+
static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
{
vlv_reserve_pctx(dev_priv, 24 << 10);
@@ -7096,17 +7088,6 @@ static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
vlv_reserve_pctx(dev_priv, 32 << 10);
}
-static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
-{
- dev_priv->gt_pm.rps.gpll_ref_freq =
- vlv_get_cck_clock(dev_priv, "GPLL ref",
- CCK_GPLL_CLOCK_CONTROL,
- dev_priv->czclk_freq);
-
- DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
- dev_priv->gt_pm.rps.gpll_ref_freq);
-}
-
static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
@@ -7114,8 +7095,6 @@ static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
valleyview_setup_pctx(dev_priv);
- vlv_init_gpll_ref_freq(dev_priv);
-
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
switch ((val >> 6) & 3) {
case 0:
@@ -7160,8 +7139,6 @@ static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
cherryview_setup_pctx(dev_priv);
- vlv_init_gpll_ref_freq(dev_priv);
-
mutex_lock(&dev_priv->sb_lock);
val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
mutex_unlock(&dev_priv->sb_lock);
@@ -7216,7 +7193,7 @@ static void cherryview_enable_rc6(struct drm_i915_private *dev_priv)
I915_WRITE(GTFIFODBG, gtfifodbg);
}
- cherryview_check_pctx(dev_priv);
+ vlv_check_pctx(dev_priv);
/* 1a & 1b: Get forcewake during program sequence. Although the driver
* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
@@ -7304,7 +7281,7 @@ static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
enum intel_engine_id id;
u32 gtfifodbg, rc6_mode = 0;
- valleyview_check_pctx(dev_priv);
+ vlv_check_pctx(dev_priv);
gtfifodbg = I915_READ(GTFIFODBG);
if (gtfifodbg) {
@@ -9287,39 +9264,31 @@ int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
{
- struct intel_rps *rps = &dev_priv->gt_pm.rps;
-
/*
* N = val - 0xb7
* Slow = Fast = GPLL ref * N
*/
- return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * (val - 0xb7), 1000);
+ return DIV_ROUND_CLOSEST(dev_priv->gpll_freq * (val - 0xb7), 1000);
}
static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
{
- struct intel_rps *rps = &dev_priv->gt_pm.rps;
-
- return DIV_ROUND_CLOSEST(1000 * val, rps->gpll_ref_freq) + 0xb7;
+ return DIV_ROUND_CLOSEST(1000 * val, dev_priv->gpll_freq) + 0xb7;
}
static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
{
- struct intel_rps *rps = &dev_priv->gt_pm.rps;
-
/*
* N = val / 2
* CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
*/
- return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * val, 2 * 2 * 1000);
+ return DIV_ROUND_CLOSEST(dev_priv->gpll_freq * val, 2 * 2 * 1000);
}
static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
{
- struct intel_rps *rps = &dev_priv->gt_pm.rps;
-
/* CHV needs even values */
- return DIV_ROUND_CLOSEST(2 * 1000 * val, rps->gpll_ref_freq) * 2;
+ return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->gpll_freq) * 2;
}
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
--
2.15.0
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