[PATCH 7/7] drm/i915: Store all the workaround types
Oscar Mateo
oscar.mateo at intel.com
Thu Oct 5 00:11:05 UTC 2017
Signed-off-by: Oscar Mateo <oscar.mateo at intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 10 +++++-----
drivers/gpu/drm/i915/i915_drv.h | 5 +++--
drivers/gpu/drm/i915/i915_workarounds.c | 34 ++++++++++++++++-----------------
3 files changed, 25 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b4a6ac6..c85e932 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3503,18 +3503,18 @@ static int i915_wa_registers(struct seq_file *m, void *unused)
intel_runtime_pm_get(dev_priv);
- seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
+ seq_printf(m, "Context workarounds applied: %d\n", workarounds->ctx_wa_count);
for_each_engine(engine, dev_priv, id)
seq_printf(m, "HW whitelist count for %s: %d\n",
engine->name, workarounds->hw_whitelist_count[id]);
- for (i = 0; i < workarounds->count; ++i) {
+ for (i = 0; i < workarounds->ctx_wa_count; ++i) {
i915_reg_t addr;
u32 mask, value, read;
bool ok;
- addr = workarounds->reg[i].addr;
- mask = workarounds->reg[i].mask;
- value = workarounds->reg[i].value;
+ addr = workarounds->ctx_wa_reg[i].addr;
+ mask = workarounds->ctx_wa_reg[i].mask;
+ value = workarounds->ctx_wa_reg[i].value;
read = I915_READ(addr);
ok = (value & mask) == (read & mask);
seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index be421f2..9d0316d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1947,8 +1947,9 @@ struct i915_wa_reg {
#define I915_MAX_WA_REGS 16
struct i915_workarounds {
- struct i915_wa_reg reg[I915_MAX_WA_REGS];
- u32 count;
+ struct i915_wa_reg ctx_wa_reg[I915_MAX_WA_REGS];
+ u32 ctx_wa_count;
+
u32 hw_whitelist_count[I915_NUM_ENGINES];
};
diff --git a/drivers/gpu/drm/i915/i915_workarounds.c b/drivers/gpu/drm/i915/i915_workarounds.c
index edbd8fc..2032b59 100644
--- a/drivers/gpu/drm/i915/i915_workarounds.c
+++ b/drivers/gpu/drm/i915/i915_workarounds.c
@@ -25,26 +25,26 @@
#include "i915_drv.h"
#include "i915_workarounds.h"
-static int wa_add(struct drm_i915_private *dev_priv,
- i915_reg_t addr,
- const u32 mask, const u32 val)
+static int ctx_wa_add(struct drm_i915_private *dev_priv,
+ i915_reg_t addr,
+ const u32 mask, const u32 val)
{
- const u32 idx = dev_priv->workarounds.count;
+ const u32 idx = dev_priv->workarounds.ctx_wa_count;
if (WARN_ON(idx >= I915_MAX_WA_REGS))
return -ENOSPC;
- dev_priv->workarounds.reg[idx].addr = addr;
- dev_priv->workarounds.reg[idx].value = val;
- dev_priv->workarounds.reg[idx].mask = mask;
+ dev_priv->workarounds.ctx_wa_reg[idx].addr = addr;
+ dev_priv->workarounds.ctx_wa_reg[idx].value = val;
+ dev_priv->workarounds.ctx_wa_reg[idx].mask = mask;
- dev_priv->workarounds.count++;
+ dev_priv->workarounds.ctx_wa_count++;
return 0;
}
#define WA_REG(addr, mask, val) do { \
- const int r = wa_add(dev_priv, (addr), (mask), (val)); \
+ const int r = ctx_wa_add(dev_priv, (addr), (mask), (val)); \
if (r) \
return r; \
} while (0)
@@ -423,7 +423,7 @@ int i915_ctx_workarounds_init(struct drm_i915_private *dev_priv)
{
int err;
- dev_priv->workarounds.count = 0;
+ dev_priv->workarounds.ctx_wa_count = 0;
if (IS_BROADWELL(dev_priv))
err = bdw_ctx_workarounds_init(dev_priv);
@@ -447,7 +447,7 @@ int i915_ctx_workarounds_init(struct drm_i915_private *dev_priv)
return err;
DRM_DEBUG_DRIVER("Number of context specific w/a: %d\n",
- dev_priv->workarounds.count);
+ dev_priv->workarounds.ctx_wa_count);
return 0;
}
@@ -457,21 +457,21 @@ int i915_ctx_workarounds_emit(struct drm_i915_gem_request *req)
u32 *cs;
int ret, i;
- if (w->count == 0)
+ if (w->ctx_wa_count == 0)
return 0;
ret = req->engine->emit_flush(req, EMIT_BARRIER);
if (ret)
return ret;
- cs = intel_ring_begin(req, (w->count * 2 + 2));
+ cs = intel_ring_begin(req, (w->ctx_wa_count * 2 + 2));
if (IS_ERR(cs))
return PTR_ERR(cs);
- *cs++ = MI_LOAD_REGISTER_IMM(w->count);
- for (i = 0; i < w->count; i++) {
- *cs++ = i915_mmio_reg_offset(w->reg[i].addr);
- *cs++ = w->reg[i].value;
+ *cs++ = MI_LOAD_REGISTER_IMM(w->ctx_wa_count);
+ for (i = 0; i < w->ctx_wa_count; i++) {
+ *cs++ = i915_mmio_reg_offset(w->ctx_wa_reg[i].addr);
+ *cs++ = w->ctx_wa_reg[i].value;
}
*cs++ = MI_NOOP;
--
1.9.1
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