[PATCH 12/22] drm/i915/guc: Introduce intel_uc_sanitize and intel_guc_sanitize

Sagar Arun Kamble sagar.a.kamble at intel.com
Thu Oct 5 11:22:05 UTC 2017


Currently GPU is reset at the end of suspend or on early resume.
On resume, GuC will not be loaded until intel_uc_init_hw happens
during GEM resume flow but action to exit sleep can be sent to GuC
considering the FW load status. To make sure we don't invoke that
action update GuC FW load status at the end of GPU reset as NONE.
load_status indicates HW state and it is sanitized through new
functions intel_uc_sanitize/intel_guc_sanitize.

v2: Rebase.

v3: Removed intel_guc_sanitize. Marking load status as NONE at the
GPU reset point. (Chris/Michal)

v4: Reinstated the uC function intel_uc_sanitize. (Michal Wajdeczko)

v5: Prepared intel_guc_sanitize. Passing engine_mask to sanitize and
updated comment. Sanitizing during guc_select_fw. (Joonas)

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko at intel.com>
Cc: MichaƂ Winiarski <michal.winiarski at intel.com>
Cc: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
---
 drivers/gpu/drm/i915/intel_guc.c        | 14 ++++++++++++++
 drivers/gpu/drm/i915/intel_guc.h        |  2 ++
 drivers/gpu/drm/i915/intel_guc_loader.c |  2 ++
 drivers/gpu/drm/i915/intel_uc.c         |  6 ++++++
 drivers/gpu/drm/i915/intel_uc.h         |  2 ++
 drivers/gpu/drm/i915/intel_uncore.c     |  2 ++
 6 files changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index bbe4c32..0d095a2 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -262,3 +262,17 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
 	i915_gem_object_put(obj);
 	return vma;
 }
+
+void intel_guc_sanitize(struct drm_i915_private *dev_priv,
+			unsigned int engine_mask)
+{
+	/*
+	 * TODO: intel_uc_resume currently depends on load_status to resume
+	 * GuC. Since we are resetting full GPU at the end of suspend, let us
+	 * mark the load status as NONE. Once intel_uc_resume is updated to take
+	 * into consideration GuC load state based on WOPCM, we can skip this
+	 * state update.
+	 */
+	if (engine_mask == ALL_ENGINES)
+		dev_priv->guc.fw.load_status = INTEL_UC_FIRMWARE_NONE;
+}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index a8a9565..1696001 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -115,6 +115,8 @@ static inline bool i915_guc_submission_enabled(struct intel_guc *guc)
 int intel_guc_suspend(struct drm_i915_private *dev_priv);
 int intel_guc_resume(struct drm_i915_private *dev_priv);
 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
+void intel_guc_sanitize(struct drm_i915_private *dev_priv,
+			unsigned int engine_mask);
 
 int intel_guc_select_fw(struct intel_guc *guc);
 int intel_guc_init_hw(struct intel_guc *guc);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 5449e5e..6214c82 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -388,6 +388,8 @@ int intel_guc_select_fw(struct intel_guc *guc)
 
 	intel_uc_fw_init(&guc->fw, INTEL_UC_FW_TYPE_GUC);
 
+	intel_guc_sanitize(dev_priv, ALL_ENGINES);
+
 	if (i915_modparams.guc_firmware_path) {
 		guc->fw.path = i915_modparams.guc_firmware_path;
 		guc->fw.major_ver_wanted = 0;
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 7305486..0cc4362 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -283,3 +283,9 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
 	if (i915_modparams.enable_guc_loading)
 		i915_ggtt_disable_guc(dev_priv);
 }
+
+void intel_uc_sanitize(struct drm_i915_private *dev_priv,
+		       unsigned int engine_mask)
+{
+	intel_guc_sanitize(dev_priv, engine_mask);
+}
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index e18d3bb..149cf03 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -34,5 +34,7 @@
 void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
 int intel_uc_init_hw(struct drm_i915_private *dev_priv);
 void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
+void intel_uc_sanitize(struct drm_i915_private *dev_priv,
+		       unsigned int engine_mask);
 
 #endif
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index b3c3f94..021081b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1763,6 +1763,8 @@ int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
 	}
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 
+	intel_uc_sanitize(dev_priv, engine_mask);
+
 	return ret;
 }
 
-- 
1.9.1



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