[PATCH v3 1/2] drm/i915: Split i915_gem_suspend into user quiescing and HW suspend

Sagar Arun Kamble sagar.a.kamble at intel.com
Sat Oct 7 19:36:53 UTC 2017


GTT mappings are to be suspended post idling GPU and display suspend.
Currently GPU was reset in i915_gem_suspend and then GTT mappings were
suspended in i915_drm_suspend. Also part of i915_gem_suspend was about
suspending HW operations. This separated the HW/GEM suspend across reset.

To achieve the complete GEM/HW suspend prior to GPU reset we need to
separate i915_gem_suspend functionality into user quiescing and HW
suspend. With this patch new function i915_gem_quiesce is created that
will ensure GEM is idle. i915_gem_hw_suspend will ensure all GPU HW
operations are suspended.

With this patch drm suspend sequence is gem_quiesce followed by
gem_hw_suspend. Unload sequence is gem_quiesce->gem_hw_suspend->gem_fini.

v2. Split i915_gem_suspend to accommodate GTT mappings suspend as that is
not to be done till display suspend. (Chris)

v3: s/i915_gem_quiescent/i915_gem_quiesce and s/i915_gem_suspend/
i915_gem_hw_suspend. gem_hw_suspend has to be done prior to gem_fini as
engine state/GuC software state would be needed to suspend HW.
s/dev_priv/i915 in i915_gem_quiesce and i915_gem_hw_suspend.
Doing GuC suspend before suspending GTT mappings as GuC needs to access
the shared data. Limiting struct_mutex lock to only gem_sanitize.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko at intel.com>
Cc: Michał Winiarski <michal.winiarski at intel.com>
Cc: Oscar Mateo <oscar.mateo at intel.com>
Cc: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 11 ++++---
 drivers/gpu/drm/i915/i915_drv.h |  3 +-
 drivers/gpu/drm/i915/i915_gem.c | 63 +++++++++++++++++++++++++----------------
 3 files changed, 48 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 66fc156..4df5caa 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -693,8 +693,9 @@ static int i915_load_modeset_init(struct drm_device *dev)
 	return 0;
 
 cleanup_gem:
-	if (i915_gem_suspend(dev_priv))
+	if (i915_gem_quiesce(dev_priv))
 		DRM_ERROR("failed to idle hardware; continuing to unload!\n");
+	i915_gem_hw_suspend(dev_priv);
 	i915_gem_fini(dev_priv);
 cleanup_uc:
 	intel_uc_fini_fw(dev_priv);
@@ -1395,9 +1396,11 @@ void i915_driver_unload(struct drm_device *dev)
 
 	i915_driver_unregister(dev_priv);
 
-	if (i915_gem_suspend(dev_priv))
+	if (i915_gem_quiesce(dev_priv))
 		DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 
+	i915_gem_hw_suspend(dev_priv);
+
 	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 
 	drm_atomic_helper_shutdown(dev);
@@ -1540,7 +1543,7 @@ static int i915_drm_suspend(struct drm_device *dev)
 
 	pci_save_state(pdev);
 
-	error = i915_gem_suspend(dev_priv);
+	error = i915_gem_quiesce(dev_priv);
 	if (error) {
 		dev_err(&pdev->dev,
 			"GEM idle failed, resume might fail\n");
@@ -1558,7 +1561,7 @@ static int i915_drm_suspend(struct drm_device *dev)
 
 	intel_suspend_hw(dev_priv);
 
-	i915_gem_suspend_gtt_mappings(dev_priv);
+	i915_gem_hw_suspend(dev_priv);
 
 	i915_save_state(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 799a90a..54a3193 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3715,7 +3715,8 @@ void i915_gem_reset_engine(struct intel_engine_cs *engine,
 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
 			   unsigned int flags);
-int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
+int __must_check i915_gem_quiesce(struct drm_i915_private *dev_priv);
+void i915_gem_hw_suspend(struct drm_i915_private *dev_priv);
 void i915_gem_resume(struct drm_i915_private *dev_priv);
 int i915_gem_fault(struct vm_fault *vmf);
 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 82a1003..f620256 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4572,54 +4572,73 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
 	}
 }
 
-int i915_gem_suspend(struct drm_i915_private *dev_priv)
+int i915_gem_quiesce(struct drm_i915_private *i915)
 {
-	struct drm_device *dev = &dev_priv->drm;
+	struct drm_device *dev = &i915->drm;
 	int ret;
 
-	intel_runtime_pm_get(dev_priv);
-	intel_suspend_gt_powersave(dev_priv);
+	intel_runtime_pm_get(i915);
 
 	mutex_lock(&dev->struct_mutex);
 
 	/* We have to flush all the executing contexts to main memory so
 	 * that they can saved in the hibernation image. To ensure the last
 	 * context image is coherent, we have to switch away from it. That
-	 * leaves the dev_priv->kernel_context still active when
+	 * leaves the i915->kernel_context still active when
 	 * we actually suspend, and its image in memory may not match the GPU
 	 * state. Fortunately, the kernel_context is disposable and we do
 	 * not rely on its state.
 	 */
-	ret = i915_gem_switch_to_kernel_context(dev_priv);
+	ret = i915_gem_switch_to_kernel_context(i915);
 	if (ret)
 		goto err_unlock;
 
-	ret = i915_gem_wait_for_idle(dev_priv,
+	ret = i915_gem_wait_for_idle(i915,
 				     I915_WAIT_INTERRUPTIBLE |
 				     I915_WAIT_LOCKED);
 	if (ret && ret != -EIO)
 		goto err_unlock;
 
-	assert_kernel_context_is_current(dev_priv);
-	i915_gem_contexts_lost(dev_priv);
+	assert_kernel_context_is_current(i915);
+	i915_gem_contexts_lost(i915);
 	mutex_unlock(&dev->struct_mutex);
 
-	intel_guc_suspend(dev_priv);
-
-	cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
-	cancel_delayed_work_sync(&dev_priv->gt.retire_work);
+	cancel_delayed_work_sync(&i915->gpu_error.hangcheck_work);
+	cancel_delayed_work_sync(&i915->gt.retire_work);
 
 	/* As the idle_work is rearming if it detects a race, play safe and
 	 * repeat the flush until it is definitely idle.
 	 */
-	drain_delayed_work(&dev_priv->gt.idle_work);
+	drain_delayed_work(&i915->gt.idle_work);
 
 	/* Assert that we sucessfully flushed all the work and
 	 * reset the GPU back to its idle, low power state.
 	 */
-	WARN_ON(dev_priv->gt.awake);
-	if (WARN_ON(!intel_engines_are_idle(dev_priv)))
-		i915_gem_set_wedged(dev_priv); /* no hope, discard everything */
+	WARN_ON(i915->gt.awake);
+	if (WARN_ON(!intel_engines_are_idle(i915)))
+		i915_gem_set_wedged(i915); /* no hope, discard everything */
+
+	intel_runtime_pm_put(i915);
+	return 0;
+
+err_unlock:
+	mutex_unlock(&dev->struct_mutex);
+
+	intel_runtime_pm_put(i915);
+	return ret;
+}
+
+void i915_gem_hw_suspend(struct drm_i915_private *i915)
+{
+	struct drm_device *dev = &i915->drm;
+
+	intel_runtime_pm_get(i915);
+	intel_suspend_gt_powersave(i915);
+
+	intel_guc_suspend(i915);
+	i915_gem_suspend_gtt_mappings(i915);
+
+	mutex_lock(&dev->struct_mutex);
 
 	/*
 	 * Neither the BIOS, ourselves or any other kernel
@@ -4640,15 +4659,11 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
 	 * machines is a good idea, we don't - just in case it leaves the
 	 * machine in an unusable condition.
 	 */
-	i915_gem_sanitize(dev_priv);
-
-	intel_runtime_pm_put(dev_priv);
-	return 0;
+	i915_gem_sanitize(i915);
 
-err_unlock:
 	mutex_unlock(&dev->struct_mutex);
-	intel_runtime_pm_put(dev_priv);
-	return ret;
+
+	intel_runtime_pm_put(i915);
 }
 
 void i915_gem_resume(struct drm_i915_private *dev_priv)
-- 
1.9.1



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