[PATCH] gtt-cache-enable

[Matthew Auld]

Signed-off-by: Matthew Auld <matthew.auld at intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9d0ca2656a23..832f21488792 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8421,6 +8421,8 @@ static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
 
 static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
+	bool can_use_gtt_cache = true;
+
 	gen9_init_clock_gating(dev_priv);
 
 	/* WaDisableSDEUnitClockGating:kbl */
@@ -8436,10 +8438,15 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
 	/* WaFbcNukeOnHostModify:kbl */
 	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
 		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
+
+	/* WaGttCachingOffByDefault:bdw */
+	I915_WRITE(HSW_GTT_CACHE_EN, can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0);
 }
 
 static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
+	bool can_use_gtt_cache = true;
+
 	gen9_init_clock_gating(dev_priv);
 
 	/* WAC6entrylatency:skl */
@@ -8449,13 +8456,15 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
 	/* WaFbcNukeOnHostModify:skl */
 	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
 		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
+
+	/* WaGttCachingOffByDefault:bdw */
+	I915_WRITE(HSW_GTT_CACHE_EN, can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0);
 }
 
 static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	/* The GTT cache must be disabled if the system is using 2M pages. */
-	bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv,
-						 I915_GTT_PAGE_SIZE_2M);
+	bool can_use_gtt_cache = true;
 	enum pipe pipe;
 
 	ilk_init_lp_watermarks(dev_priv);
-- 
2.13.6